we wanna design a fractional pll with ring oscillator.
the input frequency is from 5M to 50M, and we set the bandwith to be 50khz, the segma-delta modulator is 3th order. the current ICP is varying with the N which varies from 1 to 128
the troble we meet is by calculation the Cs in the LPF is more than 1uF!, if we want the phase margin more than 50
the other problem is the variation of bandwith is very big according the variation of N. we can't ensure that the system be stable at worst case (taking corner into account)
those are really key issues in pll design. anyone discuss this topic with me?
if N varies from 1 to 128,
the loop gain also varies from 1x to 128x,
so it's a problem,
I suggest you to use a VCO
with a 25M to 50M range,
and with dividers by 2,
you could reach 5M.
(with one divider you cover
12.5M to 25M,
and with 2 dividers, 6.25M to 12.5M
...)
Re: trobled with the system parameter design of fractional-p
aProgrammer:
thx for ur suggestion
but the spec requires N varies from 1 to 128. we tried to vary Icp with N, but it also bring a lot of problems.
i am really troubled
Re: trobled with the system parameter design of fractional-p
the bandwith variation is just one of my problems.
the huge area requred by the cap in the lpf also makes me headache. since the bandwith is set to be 50hz, the cap is as big as nF!
can active filter solve this problem? what is the disadvantage of active filter? we never do this kind of filer