I am sorry, but my English is not perfect :roll:
I want to realize this logic:
entity Three_st is
port( T: in std_logic;
I: in std_logic_vector(15 downto 0);
O: out std_logic);
end Three_st;
architecture Behav5 of Three_st is
begin
process(I,T)
begin
if (T = '0') then
O <= I;
else
O <= 'Z';
end if;
end process;
end Behav5;
I tried 5 different ways to merge all input signals to only one output, but no one was succesful :-? Please, give to me some guidance.
I know how to increase width of bus,i know how to reduce it to (0 downto 0) but i don`t know how to do the opposite when i need std_logic width only..