Hello all,
I have a question about layout best practices and if you have any issues one vs the other. Lets start with an example. I have just a sample, inverter, since NMOS and PMOS are there I can learn the new technology Layouts for DRC/LVS/ERC with nothing complicated. Now when looking at other triple well technologies, sometimes the Pcells have a TW and SUB pin. This technology I am using now does not. So normally each block I always had a VTUB and ASUB pin which I needed for the devices, then to clear ERC, I needed to correctly connect the tubs/wells/sub. Now in this technology, I could just connect up the SUB to VSS and VTUB to VDD locally and not pump it around my design, but do I want to do that? Isn't it better for noise isolation if I carry this VTUB all the way to top and connect directly to top level power routing? Also, with my ASUB, I would carry this all the way to VSS power rail right? Doesn't this create better noise isolation? Do I have to worry about poor connections to VTUB/ASUB which can result in PN diodes being forward biased during glitch events? I am just wondering, why sometimes, people say just connect locally your ASUB VTUB within a cell, while others like having them have their own pins, then a top level or chip top level, they then connect them.... Maybe its better for LVS at top level? I am wondering what are the tradeoffs here..
Kind Regards,
JGK