Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[SOLVED] Trigger detection circut..!

Status
Not open for further replies.

vjain419

Newbie level 3
Newbie level 3
Joined
Oct 31, 2011
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,300
hi..
i need verilog code for trigger detection circuit..clk,trigger_in,reset_n are input..and count_en,count_init,latch_count are output.

when trigger pulse start count_init get asserted and when it stop latch_count is assereted..and between start and stop time count_en is asserted...

i need sync_trigger pulse so i use 2 d-ff so i got sync_trigger...
i wanted out in this style..
untitled.JPG

i know i can simply use posedge of clk and sync_trigger but for my design i can only use posedge of clk so i wanted some combo logic to get it done..

that drawing is just example is mspaint so sorry for inconvience :)

regards,
vinay
 

Attachments

  • untitled.bmp
    1.9 MB · Views: 64

Is it just me, or have I seen this homework assignment before? I think it might have been one year ago or so...
 

Simplest way is FSM.

Optimal solution is also available, you have to approach your self and if there is problems, there are n number of experts available here!!!!!!!!
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top