Continue to Site

Welcome to

Welcome to our site! is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Tricky Clock Constraint Question

Not open for further replies.


Newbie level 5
Jul 5, 2011
Reaction score
Trophy points
Activity points
Hello All,

I am currently working on designing a DDR Interface from the ground up (no IP available, didn't want to go with Synopsys IP). The trouble I am having is defining clock groups.

I would like to set a clock that starts at the pin of my received strobe circuitry, this goes through some logic to delay the clock 1.5ns, from this port the clock fans out to a number of rising and falling edge flip flops. In the design I also have my system clock which comes off the board. The clocks are asynchronous. I am having a lot of difficulty setting the constraints for this situation using the commands
create_clock, set_clock_groups, and set_clock_latency. To make this slightly more difficult, the 1.5ns delayed clock is the output of a custom macro I have designed (this has with it its own lib/db). I believe the timing information is accurate, but the clock tree I am seeing does not reflect this information.

Has anyone worked with a similar problem?

Thanks for the help in advance!

Have you resolved this problem?

I think you'd better have good understing on timing constraint and SDC first.
Then you can refer to the following paper talking about DDR SDC in DC/PT:
1): Getting DDRs “write” – the 1x output circuit -- Paul Zimmer
2): Working with DDRs in PrimeTime -- Paul Zimmer

Not open for further replies.

Part and Inventory Search

Welcome to