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Yeah... PMOS can pass a strong one and a NMOS can pass a strong zero...And i am not sure whether we wont size the transistors in transmission gates....as far as i know it should be sized... size it will be uneven resistance for zeros and ones...
a common way to size transmission gate is to make both pmos and nmos the same size though this will make the rising edge delay and the falling edge delay different, but this is also true for dynamic logic and skewed cmos
this type of implementation of the Transmission Gate (by pmos and nmos) makes it suitable to be used, along with inverters, to build any two-input logic gate...and this is according to Shannon's expansion theorem:
F(A,B) = A F(1,B) + Abar F(0,B)
So if you have 2 transmission gates...the input of one of them would be connected to F(1,B) and its control is A on NMOS and Abar on PMOS...and the input of the other would be F(0,B) and its control is Abar on NMOS and A on PMOS...the output of both is just one wire=> F(A,B)...which takes its value according to the level of A