Thanks AmrZohny, I made the D-flip flop according to the schematic in the link you provided and it is working now. I am not sure why the previous arrangement was not working because that arrangement is proposed in one IEEE papers.
Amir Ghaffari, Eric, A.M. Kulmperink, "Tunable High Q N-path bandpass filters: modeling and verification" IEEE solid state circuits may 2011 (figure 18).
About your comment on non-overlapping clock generation, i am not able to get the idea. I understand that clock_positive should be equally loaded as clock_negative but what do you mean by overlapping clock generation. Is this overlapping word means that we have to give some delay between clock positive and clock negative?