Transistors are not matched in Post-layout simulation from ananotate OP

[Alex Liao]

Hi,

A current source load has two matched nmos (in figure 1) and its working OP are shown after pre-layout simulation. The OP are similar between M3D(MM0) and M4D(MM1).

But in post-layout simulation, the OP are not matched using only 2 fingers for each nmos. Please refer figure 2 for M3D and figure 3 for M4D.
First, the Vgs of MM0 is different from MM0@2 so does the id. The OP state of each finger of M3D is not the same as the other one. Second, even there is small differences of OP for each finger of M4D (MM1 and MM1@2), the M3D(MM0) is totally different from M4D(MM1) in respect to OP print.

Is there anybody who encounters those similar mismatches between schematic-level and post-layout simulation in tsmc 65nm?

Thanks,
Alex Liao

 

[Dominik Przyborowski]

In some design kits a post layout simulations OPs are related only to single finger transistors (e.g. if You have 2 fingers You can get two times lower current, etc). In addition models can include a well proximity effects - differ Vth, etc.
Unfortunately I never works with tsmc65nm - I know that this process containing halo implants so maybe it could also affects a simulations.

 

[Alex Liao]

Hi Dominik,

Thank you. I think what you have said may not be the direct reason for my case. I've tried other cases and finger number is like 15 or more. No such differences found in those cases in tsmc 65nm. It seems transistors matching in 65nm is a problem. I also tried the same case on tsmc 90nm. Only minor differences are discovered. So I am guessing that this mismatch induced by layout could happen in 65nm or more advanced technology nodes. And the direct reason is still unknown. By the way, I have closed the WPE for simplicity. Thank you for discussing with me.

Alex