The answer depends on how high the voltage is and how long the time is.
Obviously some high voltage tolerant circuit or IO used low voltage device to withstand high voltage input, JUST within a short period of time.
Normally, if you apply a DC=3.0V to a 2.5V device long enough, it will break down eventually. But it also depends on the difference of two nodes, (D, G, S, B) and any of the two nodes higher than required breakdown voltage and under prolonged time, it will break. For example, When it is NMOS, with gate biased at 2.5V, and source at 0V, bulk at 0V, and you apply 3.0V at drain, then it's not easy to break although Vds, Vdb is 3.0V, the reverse biased breakdown is much higher than 3.0V normally, typically 3 times larger than gate breakdown. Of coz, prolonged operation does effect the reliability. However, if you apply gate at 3.0 and source at 0V, the Vgs is 3.0v and as gate breakdown is much smaller, so this kind of situation cannot sustain long and will easy break after 1 day for example. For details of breakdown voltage, you need to consult the foundry and they can do MEDICI simulation to confirm this or have some experiement results about this