Transformer flux balancing in full bridge smps?

[treez]

Hello,
On page 9 of Dr Ray Ridley's book, Dr Ridley states that "transformer flux balancing" is a thing that one should be wary of in a full bridge converter.
What does he mean by this?
I mean, surely, if one has primary current sensing via a current sense transformer, then it isn't going to be a problem?
Also, if one ensures that at the maximum on_time of the fet, the primary magnetising current cant rise to saturation level, then surely there will never be a problem with flux balancing?

I have never seen such a problem demonstrated in a simulation , and can't believe its actually a problem?

 

[std_match]

I don't have the book, but I think I understand what he means. Since the flux is driven actively in both directions, it is very important that the mean is zero.
The "on time" and the driving voltage must be equal in both directions, otherwise the "mean flux" will move away from zero and cause problems.
If the flux isn't balanced, the "on current" will not be the same in both directions. The transformer losses will increase and the maximum power will decrease.

The "problem" is restricted to the primary side. The secondary side has nothing to do with "flux balancing" in a full bridge converter.

 

[treez]

thanks, the thing is , as you allude, the on times don't change quickly, (due to the feedback compensation capacitors) and so adjacent fet on_times would never be different enough to cause flux imbalance, so what on earth Dr Ridley is on about I will never know.?

 

[FlapJack]

My guess is Ridley was taking about voltage mode control being a problem.

 

[treez]

indeed maybe so, but I don't see it being a problem in voltage mode...maybe in a burst mode converter, or some such where adjacent duty cycles could vary widely in time?

 

[schmitt trigger]

Transformer flux balance considerations are most important on the push pull topology, but could also happen in a bridge, at least on theory.

The transistor pairs on one side could have slightly higher RDSon than the other pair, and thus for a fixed duty cycle, a slightly lower volt-time will be applied. If this continues for many cycles, it could lead to staircase saturation.

 

[mtwieg]

indeed maybe so, but I don't see it being a problem in voltage mode...maybe in a burst mode converter, or some such where adjacent duty cycles could vary widely in time?

It's not something that would happen in a simulation unless you actually went to the trouble of forcing unbalanced drive of the transformer. In reality this occurs due to tolerances in the FETs, gate drivers, etc. In decades past it was a much more severe issue when BJTs were standard, but MOSFETs have much more consistent switching characteristics.

 

[treez]

Actually I have just found a very good reason why Dr Ridley might be very correct about full bridge transformer imbalance.......when you have a full bridge with a duty cycle of above 0.5, then during start-up, the adjacent primary current pulses can be vastly different in length, (subharmonic oscillation) and this can be so for many many cycles.........ie, going one way through the primary, the current pulse is wide, then going the other way, it is always narrow......BANG!.....the following LTspice simulation, as attached, demonstrates this.......I fear now that the full bridge is indeed not safe for duty cycles above 0.5, due to subharmonic oscillation, because even with slope compensation, during start up, subharmonic oscillation still happens....just take a look yourself, -this could consign the full bridge to the history books for duty cycles above 0.5.....

 

[schmitt trigger]

I attempted to open up the attached file, but gives me the error warning: multiple instances of "flag".

 

[FvM]

How could a simulation circuit with fixed gate control waveforms show subharmonic oscillations? Of course it doesn't. You see a transient inrush current while charging the secondary capacitors.

You may get the problem with unsuitable current feedback design.

 

[treez]

my apolgies , please find here the LTspice simulation which I should have put in post #8.
It shows the adjacent gate pulses of vastly different length...causing staircase saturation of the transformer

 

[FvM]

I believe that assymmetry might happen, but I don't see it in this simulation. I also assume that the LTC3723 slope compensation circuit can suppress it if dimensioned appropriately.