jdshah
Junior Member level 3
Hello,
I do not completely understand use of tran keyword in verilog.
Example :
tran c (a,b);
Explanation says
The tran switch acts as a buffer between the two signals a and b. Either a
or b can be the driver signal.
My question is if a and b both are connected to some different signal, who will decide which will be the driver signal. Who will win?
I do not completely understand use of tran keyword in verilog.
Example :
tran c (a,b);
Explanation says
The tran switch acts as a buffer between the two signals a and b. Either a
or b can be the driver signal.
My question is if a and b both are connected to some different signal, who will decide which will be the driver signal. Who will win?