To support SystemVerilog, most tools require that your files have a *.sv file extension. They may also have a global switch (ModelSim has -sv) that makes it treat all Verilog files as SystemVerilog, but I strongly recommend not using that switch as some legacy Verilog files will not compile in SystemVerilog mode because of newly reserved keywords.
If that does not help you, we would be able to help you much better if you posted the exact error message you are getting.