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Tools supporting verilog-2001

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anusha vasanta

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Hi all,
i am using xilinx tools for my rtl implementation. what versions of isim do support verilog 2001 also.because i was using xilinx 13.3 in that it was saying that part select of memory is not possible. but, actually our 2001 will support this know. anyone help me.
thanx in advance
 

verylsi

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Hi Anusha,

13.3 supports verilog 2001, also the "part select" ( +: ) was added in Verilog 2000, The Isim should support this.
 

mrflibble

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ISE 13.3 supports that AFAIK. Please post the error messages, so there's no confusion as to what the problem is..
 

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I tested the following part select usage in ISE 13.2 (which I happened to have installed).

Code:
always @ (posedge clk) begin
  for (i=0;i<8;i=i+1) begin
    a_bytes[i] <= a[8*i +:8];
  end
end
this worked without any problem, I think you need to post the entire error line and your code.
 

anusha vasanta

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thanku all for your support,
the doubt is cleared. but there was a problem when i wanted to simulate my s.v code.previously i had done all the flow using synopsys tool but as it is for fpga purpose i was using model-sim and isim but they are not supporting my sv code. or else i don't know whether i was wrong. suggest me which version of xilinx and modelsim support s.v.
thanx in advance
 

dave_59

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To support SystemVerilog, most tools require that your files have a *.sv file extension. They may also have a global switch (ModelSim has -sv) that makes it treat all Verilog files as SystemVerilog, but I strongly recommend not using that switch as some legacy Verilog files will not compile in SystemVerilog mode because of newly reserved keywords.

If that does not help you, we would be able to help you much better if you posted the exact error message you are getting.
 

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Xilinx tools are notoriously bad with SV support. My advice don't use any SV unless you verify it works with the tools. You'll also either have to use the -sv switch when compiling the specific file or use an .sv file extenstion when using ISIM or Vivado's XSIM. For XST (or Vivado) synthesis you'll likely find that there are a lot of synthesizable SV things that just throws errors. I pretty much gave up with trying to use SV with Xilinx tools since ISE 13.3. I tried again with Vivado, but had very mixed results. FWIW the Vivado tools didn't even have the -sv switch documented for one of the tools (don't recall which one)
 
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