just a summary of all the post above.
For verification, the most relevant languages are:
Verilog/VHDL (the implementation or the language for DUT)
SystemC, SystemVerilog, Vera, e language (these for test benches)
Of course, following languages are also important:
C/C++ (C++ is the basis of SystemC, and C/C++ is the major coding language for VPI)
PLI/DPI/VPI are the programmable interfaces, they are extreme useful when the simulator cannot directly support SystemC/SystemVerilog or some special functions are needed. But in normal cases, you dont need to produce PLI/DPI/VPI from scratch as they are provided.
Perl/Tcl/Bash/Lisp these are script language. They are extremely useful when you want to automise your verification whichout human interaction. From a strict point of view, they are not directly relevent to verification as they are usually required by all EDA tool flow.
Matlab/SPW These are high-level prototype tools used by architects. It is desirable for verification engineers to understand them but not essential.
Something about concepts:
OVM/UVM/VMM these are verification methodologies rather than languages. It is quite important for good verification engineers to follow them.