AllenD
Member level 5
Too much vias in layout? Whats the consequences?
Hi My friends,
In an IC layout, is there such thing as too many vias?
I am using TSMC 65 nm CMOS to layout some circuit. My methods to place vias is "as much as possible" so that the resistance will be smaller. As the result, there are a LOT of vias in the layout. However, an experenced designer in my lab told me he would not place so much vias. He could not conclusively know what will be the consequences expect potential metal density failure.
Can anyone help me? If there are too many vias, what could go wrong?
Thanks
Allen
Hi My friends,
In an IC layout, is there such thing as too many vias?
I am using TSMC 65 nm CMOS to layout some circuit. My methods to place vias is "as much as possible" so that the resistance will be smaller. As the result, there are a LOT of vias in the layout. However, an experenced designer in my lab told me he would not place so much vias. He could not conclusively know what will be the consequences expect potential metal density failure.
Can anyone help me? If there are too many vias, what could go wrong?
Thanks
Allen