Re: Too much vias in layout? Whats the consequences?
This depends on the vias and the next layer of metal.
I have worked in hot-dep aluminum technologies where
(say) Met2 is the source for Via1 fill. Works well when it
works well. When it does not, the vias draw too much
material from the flat field and you get sidewalls that are
too thin or even voided.
This drove special large-bed via rules (>2x2 arrays) that
require more spacing, so as to enforce more accessible
fill-volume and more repeatable filling.
This issue was discovered at FOK fab on a DX federal
program, with predictable levels of joy and camaraderie.
I had to go and ream out every via-bed in the power
grid by hand, cutting quantity by half (fortunately my
layout style is to put as many vias as will fit the bussing
so that I get less density rule knocks).
Tungsten-plug vias as are common in more modern CMP
stacks, don't want anything from the abutting layers.
This has its own electromigration consequences (which
may or may not be properly characterized or expressed
in the layout rules).
In newer technologies you may see max as well as min
layer density rules and furthermore, these may be small-
field / "porthole" (not chip extent) based, if there are
any known lithography issues attending high density
(min density is often more about auto-align goings-on,
at least for negative features; positive features also may
have over-etch concerns). Sometimes "lonely vias" are
also probe to overetch, or a process tuned for the
"lonely" via may then underetch in large beds or high
density routing.
CMP interconnect doesn't suffer the current-flow
disturbance / crowding as much as non-planarized (non-
plug) via fills, there is no sidewall "choke point".