To script critical paths until slack is met..

[cherizkrish]

After clock_opt,
When i did report_timing, i got Worst slack (violated) 1.5ns..


****************************************
Report : timing
-path full
-delay max
-max_paths 1
Design : aes
Version: D-2010.03-ICC-SP4
Date : Sat Jun 1 16:12:49 2013
****************************************


Operating Conditions: slow Library: NangateOpenCellLibrary
Parasitic source : LPE
Parasitic mode : RealRC
Extraction mode : MAX
Extraction derating : 125/125/125

Information: Percent of Arnoldi-based delays = 11.91%

Information: Percent of CCS-based delays = 11.91%

Startpoint: D_CONTROL_addr_reg_1_
(rising edge-triggered flip-flop clocked by clk)
Endpoint: D_RAM/clk_gate_ram1_reg_18_/latch
(gating element for clock clk)
Path Group: clk
Path Type: max

Point Incr Path
--------------------------------------------------------------------------
clock clk (rise edge) 0.00 0.00
clock network delay (propagated) 2.08 2.08
D_CONTROL_addr_reg_1_/CK (DFFS_X2) 0.00 2.08 r
D_CONTROL_addr_reg_1_/QN (DFFS_X2) 0.60 2.69 r
D_RAM/addr_a[1] (ram_model_1) 0.00 2.69 r
D_RAM/U273/ZN (INV_X2) 0.13 * 2.81 f
D_RAM/U272/ZN (NOR3_X4) 0.46 * 3.28 r
D_RAM/U8750/Z (BUF_X4) 0.59 * 3.87 r
D_RAM/U8739/Z (BUF_X4) 0.75 * 4.62 r
D_RAM/U8736/Z (BUF_X4) 0.72 * 5.34 r
D_RAM/U8735/ZN (INV_X4) 0.09 * 5.44 f


D_RAM/U449/ZN (NOR2_X1) 2.28 * 7.71 r


D_RAM/clk_gate_ram1_reg_18_/EN (SNPS_CLOCK_GATE_HIGH_ram_model_147) 0.00 7.71 r
D_RAM/clk_gate_ram1_reg_18_/latch/E (CLKGATETST_X2) 0.01 * 7.72 r
data arrival time 7.72

clock clk (rise edge) 6.00 6.00
clock network delay (propagated) 0.90 6.90
D_RAM/clk_gate_ram1_reg_18_/latch/CK (CLKGATETST_X2) 0.00 6.90 r
clock gating setup time -0.71 6.18
data required time 6.18
--------------------------------------------------------------------------
data required time 6.18
data arrival time -7.72
--------------------------------------------------------------------------
slack (VIOLATED) -1.5




I do upsize a particular cell by below command
size_cell U449 [get_lib_cells */NOR2_X2]

This slack is gone...
But i do get a different slack say -1.38ns in some other critical path..


So here is my question-

I do report_timing, a WNS occurred in my design and i reduce it by up-sizing my particular cell which has highest delay..
And further i do report_timing, yet again i get WNS(less than the first iteration) in design and i need to reduce it by sizing a cell which contributes more delay...


Is it possible to script so that, we find the highest delay of cell when we do report_timing and size that particular cell and continue until the slack is met..????

PS: I am new to PD.. putting loads of effort to know much more.. Any kind of guidance is highly appreciated..

Thanks

 

[rca]

In primetime, you have some command to fix that "easily": fix_eco_drc, and could generate a script which indicate what modification was made by the command.