I think you are getting the concept of latency wrong. When you are doing early estimation or even logical synthesis, you use latency as a placeholder for the actual insertion delay of the clock tree. Later, when implementation is taking place, the latency you set is replaced by the actual obtained latency of the tree.
If you are doing something to get the timing MET on idea STA report, it mean other clock latencies are "0", and memory_clock latency is "-0.7".
If you realy need that latency skew, you can make the constraint on CTS step. ICC can handle to make that skew later on.