Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

to get an idea about cic filters

Status
Not open for further replies.

kannan2590

Member level 4
Joined
Sep 1, 2012
Messages
77
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Location
india
Activity points
2,321
CIC_interpolator.svg.png
From the attached image of cic filter can any body give idea about to write vhdl code for cic filter.
 

Referring to a previous thread of yours
i have studied meyer bases book on "dsps with Fpga" . I want the block diagram of cic interpolation . At the same time can anybody give the idea about how to write a vhdl code for the cic interpolation filter.
There are VHDL code examples in the book. Others have been posted at Edaboard before, and much more can be found on the web.
 

Referring to a previous thread of yours

There are VHDL code examples in the book. Others have been posted at Edaboard before, and much more can be found on the web.

I am attaching an file in that see the bit growth part and can you tell me to handle 48 bits is it possible in vhdl coding especially for fpga device.Is there an ip core to do this accumulation job so that we need not write code for cic comb and integrator sections?
 

Attachments

  • cic2.pdf
    130.9 KB · Views: 73
  • CIC_interpolator.svg.png
    CIC_interpolator.svg.png
    9.7 KB · Views: 126
  • 00466647.pdf
    931.9 KB · Views: 82

The full bit width will be only needed in the first integrator stage, in the succeeding stages it can be reduced according to Hogenauers pruning calculation based on SNR condiderations. 48 bits isn't a problem for VHDL adders/subtractors.

I don't see the second paper related to CIC design at all, it's talking about multiplier resource reuirements of FIR filters.

FPGA vendors like Altera and Xilinx have CIC IP that's easy to use. In my view, a basic CIC can be coded from the scratch without much problems. I also did it when I started with CIC many years ago.
 

The full bit width will be only needed in the first integrator stage, in the succeeding stages it can be reduced according to Hogenauers pruning calculation based on SNR condiderations. 48 bits isn't a problem for VHDL adders/subtractors.

I don't see the second paper related to CIC design at all, it's talking about multiplier resource reuirements of FIR filters.

FPGA vendors like Altera and Xilinx have CIC IP that's easy to use. In my view, a basic CIC can be coded from the scratch without much problems. I also did it when I started with CIC many years ago.

Can you give me the code for cic filter which you have did?
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top