kannan2590
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There are VHDL code examples in the book. Others have been posted at Edaboard before, and much more can be found on the web.i have studied meyer bases book on "dsps with Fpga" . I want the block diagram of cic interpolation . At the same time can anybody give the idea about how to write a vhdl code for the cic interpolation filter.
Referring to a previous thread of yours
There are VHDL code examples in the book. Others have been posted at Edaboard before, and much more can be found on the web.
The full bit width will be only needed in the first integrator stage, in the succeeding stages it can be reduced according to Hogenauers pruning calculation based on SNR condiderations. 48 bits isn't a problem for VHDL adders/subtractors.
I don't see the second paper related to CIC design at all, it's talking about multiplier resource reuirements of FIR filters.
FPGA vendors like Altera and Xilinx have CIC IP that's easy to use. In my view, a basic CIC can be coded from the scratch without much problems. I also did it when I started with CIC many years ago.