If you synthesize this code in Xilinx ISE 8.1 you will be able to reproduce the following error:
ERROR:Xst:850 - "top.v" line 28: Unsupported Switch or UPD primitive.
Please let me know if its ok to declare a UDP outside a module in any Verilog_Module.v source or there is there something wrong with this declaration...
I tried declaring the UDP with in the module and that did not work either...
Appreciate for your time and help.
No, as of now the only tool I have access to is Xilinx ISE 8.1. What other tools are you looking at??? I think it should work even on Xilinx ISE cuz I have pulled up the example code from Xilinx web resources...
This information can be found here: **broken link removed**.