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[TimingClosure] Pre- & Post- P&R logic synthesis

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ivlsi

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Hello All,

Can Back-End tools do a logic synthesis / timing optimization? Which of tools can do so?

Why a logic synthesis by RTL designers is needed? Why not to pass the RTL code directly to the Back-End group just after functional verification?

Thank you!
 

I have not used back-end tools for logic synthesis. In my experience that would be an unusual design flow and I'm not aware of any back-end tools that do that. At the pre-ECO stage, front end designers synthesize the logic and hand off the netlists to the physical design team. This is probably done because RTL designers have more front end/synthesis experience and physical designers already have enough to do without taking on the extra responsibility of logic synthesis.
Typically the back-end tools only do timing optimizations: resize cells, re-route wires, add/remove buffers, etc.
 

Let us agree on Sub steps in various stages you mentioned... Synthesis: Translation followed by Optimization followed by Mapping
Back end stage/work/group activities.. Placement, CTS, Routing, DRC/LVS & extraction. Timing/Area/Test/yield Optimizations and capping it with DRC/LVS & extraction.

If RTL is fed to synthesis tool, then degrees of freedom to optimize are lot higher. (In big part due to so called high Level Optimizations like resource sharing etc). However, once mapped to netlist, Options to optimize are that much limited. (as refered comments by gliss). Conceptually, we can have a chip_compiler or make_chip which has right combination of algorithms in a huge tool. But market has not developed that way. There is Front end, and there is back end and they touch each other but not merge.
 

Back end tools are designed in such away to start optimization from the technology mapped gates. There is no provision to read Technology independent RTL into Back end tools.

you can recommend synopsys or cadence for scuh types if cost is not the factor. The logic synthesis tools are cheper compared to backend tools.

regards, Sam
 

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