Let us agree on Sub steps in various stages you mentioned... Synthesis: Translation followed by Optimization followed by Mapping
Back end stage/work/group activities.. Placement, CTS, Routing, DRC/LVS & extraction. Timing/Area/Test/yield Optimizations and capping it with DRC/LVS & extraction.
If RTL is fed to synthesis tool, then degrees of freedom to optimize are lot higher. (In big part due to so called high Level Optimizations like resource sharing etc). However, once mapped to netlist, Options to optimize are that much limited. (as refered comments by gliss). Conceptually, we can have a chip_compiler or make_chip which has right combination of algorithms in a huge tool. But market has not developed that way. There is Front end, and there is back end and they touch each other but not merge.