Chinmaye
Full Member level 3
Dear all,
I am trying to synthesis my verilog code to check the slack. But the timing slack shows unconstrained. Attaching the declarations in my top module and constraints file.
View attachment top_main.txt
View attachment constraints_top.txt
I am trying to synthesis my verilog code to check the slack. But the timing slack shows unconstrained. Attaching the declarations in my top module and constraints file.
View attachment top_main.txt
View attachment constraints_top.txt