Hi,
I need some advices for my RTL design.
Is there any differences about timing performance between these two coding style below?
Does the second coding style have a better timing performance?
Many years ago, the synthesis tool(DC) put a buffer on every assign statement and it would have made some difference in timing, but now a synthesis tool is much more sophisticated and I believe it probably doesn't make difference(but no proof for that).
Thank you so much!
I've just moved to ASIC design from FPGA design. Before, I met timing issue with this coding style on FPGA.
So it makes me confuse. Your answer helps me a lot.