Timing loop detected warning in a synthesis report

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urakiki

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Hi All,

I found the warning about the timing loop detecteds in my synthesis report. What is this warning mean? Is this a critical warning? How to solve it?

Can someone explain some theory on the timing loop issue.

thanks
 

timing loop detected

It could be a bug in your design, if you didn't intend to create a combinatorial feedback loop. Does the warning message tell you which signal is looping?

I found these words somewhere:
"Combinatorial timing loops: These loops are created when output of combinatorial logic or gate is fed back to its input making a timing loop. This kind of loops unnecessary increase the number of cycles by infinitely going around the circle in the same path. These loops also cause a problem in testability."
 
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