TIming logic implementation in virtuoso

[VirtuosoDracula]

Hi All,

I'm making a design in which I need to make signal B of pulse width p2,go active, after signal A of pulse p1 has gone low and so on for signal C.
Any ideas of how to implement that in Virtuoso?

Thanks in advance,
VD

 

[erikl]

This is not a question of Virtuoso implementation, it's a logic circuit design task.