sreevenkjan
Full Member level 5
Hey Guys,
I have attached a simulation screenshot of my VHDL program. The output data is 0 in the beginning and is not synchronous with input. I am using a ROM as LUT which is initialised with my .mif file. While I am not able to sync the output (data_out) and input (data_in), the end output data after implementation looks shifted. Could you tell me where am I doing wrong and how can I fix it??
![image.png image.png](https://www.edaboard.com/data/attachments/54/54385-a75da5edfd3745399bd5978bc77959f7.jpg)
I have attached a simulation screenshot of my VHDL program. The output data is 0 in the beginning and is not synchronous with input. I am using a ROM as LUT which is initialised with my .mif file. While I am not able to sync the output (data_out) and input (data_in), the end output data after implementation looks shifted. Could you tell me where am I doing wrong and how can I fix it??
![image.png image.png](https://www.edaboard.com/data/attachments/54/54385-a75da5edfd3745399bd5978bc77959f7.jpg)
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