Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

[SOLVED] Timing Issue between Input and Output

Status
Not open for further replies.
S

sreevenkjan

Full Member level 5
Joined
Nov 4, 2013
Messages
268
Helped
27
Reputation
54
Reaction score
26
Trophy points
1,308
Location
Germany
Activity points
3,115
Hey Guys,

I have attached a simulation screenshot of my VHDL program. The output data is 0 in the beginning and is not synchronous with input. I am using a ROM as LUT which is initialised with my .mif file. While I am not able to sync the output (data_out) and input (data_in), the end output data after implementation looks shifted. Could you tell me where am I doing wrong and how can I fix it??

image.png
 
Last edited:

The problem is in your code. In order to fix it, you'll need to change the code.

Kevin
 

K-J said:
The problem is in your code. In order to fix it, you'll need to change the code.

Kevin
Click to expand...

Yes you are right the problem is in the code. Could you please elaborate about the problem?? I am not to find out where the problem is. Can the latency be due to the ROM IP functioning of Altera??
 

A wavedorm is not your code, without the code nobody is going to be able to help you.
Post your code (using syntax tags) and then we can try helping you.
 

sreevenkjan said:
Yes you are right the problem is in the code. Could you please elaborate about the problem?? I am not to find out where the problem is.
Click to expand...
Assuming you've written this in VHDL, you'll find the problem in the architecture section, not in the entity.
Can the latency be due to the ROM IP functioning of Altera??
Click to expand...
No

Kevin
 

@KJ and ads-ee - Thank you. Well I changed the code and now the output is better than the previous one.

image1.png

However could you tell me why my data_out signal reads '0' in the first clock signal?
 

Porbably because thats what the registers are initialised to.
 

The registers are not assigned to any values. I have attached the code below.

Code: 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;

-- Entity Declaration

ENTITY gamma IS
	PORT
	(
		clk			: IN STD_LOGIC;
		rst			: IN STD_LOGIC;
		data_in		: IN STD_LOGIC_VECTOR(159 downto 0);
		data_out		: OUT STD_LOGIC_VECTOR(159 downto 0);
		fval_in		: IN STD_LOGIC;
		lval_in		: IN STD_LOGIC;
		dval_in		: IN STD_LOGIC;
		fval_out 	: OUT STD_LOGIC;
		lval_out 	: OUT STD_LOGIC;
		dval_out 	: OUT STD_LOGIC
	); 
END gamma;

-- Architecture of Gamma

ARCHITECTURE behav of gamma IS

-- gamma_lut1 component

COMPONENT gamma_lut1
PORT (
			address	: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
			clock		: IN STD_LOGIC;
			q			: OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
	);
END COMPONENT;

-- gamma_lut2 component

COMPONENT gamma_lut2
PORT (
			address	: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
			clock		: IN STD_LOGIC;
			q			: OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
	);
END COMPONENT;

-- gamma_lut3 component

COMPONENT gamma_lut3
PORT (
			address	: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
			clock		: IN STD_LOGIC;
			q			: OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
	);
END COMPONENT;

-- gamma_lut4 component

COMPONENT gamma_lut4
PORT (
			address	: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
			clock		: IN STD_LOGIC;
			q			: OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
	);
END COMPONENT;

-- gamma_lut5 component

COMPONENT gamma_lut5
PORT (
			address	: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
			clock		: IN STD_LOGIC;
			q			: OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
	);
END COMPONENT;

-- gamma_lut6 component

COMPONENT gamma_lut6
PORT (
			address	: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
			clock		: IN STD_LOGIC;
			q			: OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
	);
END COMPONENT;

-- gamma_lut7 component

COMPONENT gamma_lut7
PORT (
			address	: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
			clock		: IN STD_LOGIC;
			q			: OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
	);
END COMPONENT;

-- gamma_lut8 component

COMPONENT gamma_lut8
PORT (
			address	: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
			clock		: IN STD_LOGIC;
			q			: OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
	);
END COMPONENT;

-- gamma_lut9 component

COMPONENT gamma_lut9
PORT (
			address	: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
			clock		: IN STD_LOGIC;
			q			: OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
	);
END COMPONENT;

-- gamma_lut10 component

COMPONENT gamma_lut10
PORT (
			address	: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
			clock		: IN STD_LOGIC;
			q			: OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
	);
END COMPONENT;

-- gamma_lut11 component

COMPONENT gamma_lut11
PORT (
			address	: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
			clock		: IN STD_LOGIC;
			q			: OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
	);
END COMPONENT;

-- gamma_lut12 component

COMPONENT gamma_lut12
PORT (
			address	: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
			clock		: IN STD_LOGIC;
			q			: OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
	);
END COMPONENT;

COMPONENT gamma_lut13
PORT (
			address	: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
			clock		: IN STD_LOGIC;
			q			: OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
	);
END COMPONENT;

-- gamma_lut10 component

COMPONENT gamma_lut14
PORT (
			address	: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
			clock		: IN STD_LOGIC;
			q			: OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
	);
END COMPONENT;

-- gamma_lut11 component

COMPONENT gamma_lut15
PORT (
			address	: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
			clock		: IN STD_LOGIC;
			q			: OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
	);
END COMPONENT;

-- gamma_lut12 component

COMPONENT gamma_lut16
PORT (
			address	: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
			clock		: IN STD_LOGIC;
			q			: OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
	);
END COMPONENT;

	BEGIN

	-- instantiating gamma_lut1
	
	lut1 : gamma_lut1
		port map(
			address	=> data_in(9 downto 0),
			clock		=> clk,
			q			=> data_out(9 downto 0)
		);
		
	-- instantiating gamma_lut2

	lut2 : gamma_lut2
		port map(
			address	=> data_in(19 downto 10),
			clock		=> clk,
			q			=> data_out(19 downto 10)
		);
		
	-- instantiating gamma_lut3

	lut3 : gamma_lut3
		port map(
			address	=> data_in(29 downto 20),
			clock		=> clk,
			q			=> data_out(29 downto 20)
		);
		
	-- instantiating gamma_lut4

	lut4 : gamma_lut4
		port map(
			address	=> data_in(39 downto 30),
			clock		=> clk,
			q			=> data_out(39 downto 30)
		);
		
	-- instantiating gamma_lut5

	lut5 : gamma_lut5
		port map(
			address	=> data_in(49 downto 40),
			clock		=> clk,
			q			=> data_out(49 downto 40)
		);
		
	-- instantiating gamma_lut6

	lut6 : gamma_lut6
		port map(
			address	=> data_in(59 downto 50),
			clock		=> clk,
			q			=> data_out(59 downto 50)
		);
		
	-- instantiating gamma_lut7

	lut7 : gamma_lut7
		port map(
			address	=> data_in(69 downto 60),
			clock		=> clk,
			q			=> data_out(69 downto 60)
		);
		
	-- instantiating gamma_lut8

	lut8 : gamma_lut8
		port map(
			address	=> data_in(79 downto 70),
			clock		=> clk,
			q			=> data_out(79 downto 70)
		);
		
	-- instantiating gamma_lut9

	lut9 : gamma_lut9
		port map(
			address	=> data_in(89 downto 80),
			clock		=> clk,
			q			=> data_out(89 downto 80)
		);
		
	-- instantiating gamma_lut10

	lut10 : gamma_lut10
		port map(
			address	=> data_in(99 downto 90),
			clock		=> clk,
			q			=> data_out(99 downto 90)
		);
		
	-- instantiating gamma_lut11

	lut11 : gamma_lut11
		port map(
			address	=> data_in(109 downto 100),
			clock		=> clk,
			q			=> data_out(109 downto 100)
		);
		
	-- instantiating gamma_lut12

	lut12 : gamma_lut12
		port map(
			address	=> data_in(119 downto 110),
			clock		=> clk,
			q			=> data_out(119 downto 110)
		);
		
	-- instantiating gamma_lut13

	lut13 : gamma_lut13
		port map(
			address	=> data_in(129 downto 120),
			clock		=> clk,
			q			=> data_out(129 downto 120)
		);
		
	-- instantiating gamma_lut14

	lut14 : gamma_lut14
		port map(
			address	=> data_in(139 downto 130),
			clock		=> clk,
			q			=> data_out(139 downto 130)
		);
		
	-- instantiating gamma_lut15

	lut15 : gamma_lut15
		port map(
			address	=> data_in(149 downto 140),
			clock		=> clk,
			q			=> data_out(149 downto 140)
		);
		
	-- instantiating gamma_lut16

	lut16 : gamma_lut16
		port map(
			address	=> data_in(159 downto 150),
			clock		=> clk,
			q			=> data_out(159 downto 150)
		);
	

	gamma_process : process(rst,fval_in,dval_in,lval_in)
	
	BEGIN
		
		if rst = '1' then
			fval_out <= '0';
			lval_out <= '0';
			dval_out <= '0';
		else
			fval_out <= fval_in;
			lval_out <= lval_in;
			dval_out <= dval_in;
		end if;

			
	end process;
	
END behav;

I implemented the block in the main program and could see having sync issues. The output seems to be shifted by one clock cycle.
 

The waveform is somehow misleading, because the lval_xx and fval_xx signals are completely unrelated to the lut signals.

What you see is simply the output of a synchronous block RAM, clk, address input and data outputs are only passed through the shown entity. By nature of synchronous RAM, the data is available in the next clock cycle after applying the address. It's not clear what's your problem in this regard. I suspect a general problem in understanding synchronous logic operation.
 

FvM said:
The waveform is somehow misleading, because the lval_xx and fval_xx signals are completely unrelated to the lut signals.

What you see is simply the output of a synchronous block RAM, clk, address input and data outputs are only passed through the shown entity. By nature of synchronous RAM, the data is available in the next clock cycle after applying the address. It's not clear what's your problem in this regard. I suspect a general problem in understanding synchronous logic operation.
Click to expand...

@ FvM

the lval and fval signals are not related to LUT signals as u have mentioned. Well my question was why does the output shown as '0' in the the simulation diagram, even though I am not assigning output as '0'. While implementing the current block in the main project, the data_output in being is '0' and the data is shifted towards the right. So my question is how can I solve this problem??
 

You dont assign the data_out a value, the synchronous rams do. They Cannot output a value until the first clock has occured, ie. they have a latency of 1 clock from address in to data out (as is normal for synchronous rams.

As FvM suggests - I think it's your misunderstanding of synchronous logic.
 

Besides what Tricky has stated the gamma_lut## components probably have an initial value assigned to the output register of the RAM/ROM block, therefor you see a 0 at the start of simulation and the new data showing up at the next clock cycle.

I wonder if you have a problem in your testbench in the generation of the data_in (the LUT address) value as the data_out (LUT output) value (from a clocked RAM/ROM) changes at the same time as data_in. I suspect you didn't generate data_in using the clock used to drive the RAMs and are seeing a simulation scheduling problem, due to a bad testbench design.
 

Thanks. I was not aware of this latency of 1 clock cycle. How can I improve the timing??
 

Pipeline the design to align stuff with each other, i.e. add registers to compensate for the RAM/ROM delay.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top