Timing information during synthesis

shobanaganesan · Jan 19, 2015

I have synthesised the following code in Xilinx ISE PROJECT NAVIGATOR 14.6...The synthesis results show that
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: No path found..
How can this be possible..
The code is posted here..

Code:

module sisored(clk,transmitted_data,detected_data);
  input clk;
  input [31:0]transmitted_data;
  output [31:0]detected_data;
  wire [31:0]wout,xout,yout,zout;    
  wire [31:0]r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15,r16;
  wire [31:0]i1,i2,i3,i4,i5,i6,i7,i8,i9,i10,i11,i12,i13,i14,i15,i16;
  wire [31:0]ar1,ai1,ar2,ai2,ar3,ai3,ar4,ai4,ar5,ai5,ar6,ai6,ar7,ai7,ar8,ai8,ar9,ai9,ar10,ai10,ar11,ai11,ar12,ai12,ar13,ai13,ar14,ai14,ar15,ai15,ar16,ai16;
   
  assign transmitted_data=32'b01101101101101101101101101101101;
   modqpskRX qpskmod(32'b01101101101101101101101101101101,ar1,ai1,ar2,ai2,ar3,ai3,ar4,ai4,ar5,ai5,ar6,ai6,ar7,ai7,ar8,ai8,ar9,ai9,ar10,ai10,ar11,ai11,ar12,ai12,ar13,ai13,ar14,ai14,ar15,ai15,ar16,ai16);
   channel t(ar1,ai1,ar2,ai2,ar3,ai3,ar4,ai4,ar5,ai5,ar6,ai6,ar7,ai7,ar8,ai8,ar9,ai9,ar10,ai10,ar11,ai11,ar12,ai12,ar13,ai13,ar14,ai14,ar15,ai15,ar16,ai16,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15,r16,i1,i2,i3,i4,i5,i6,i7,i8,i9,i10,i11,i12,i13,i14,i15,i16);
   //receiver
  rec rece(clk,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15,r16,i1,i2,i3,i4,i5,i6,i7,i8,i9,i10,i11,i12,i13,i14,i15,i16,wout,xout,yout,zout);
  compare cm1(wout,xout,yout,zout,detected_data);
endmodule

//qpsk modulation:
module modqpskRX(b,ar1,ai1,ar2,ai2,ar3,ai3,ar4,ai4,ar5,ai5,ar6,ai6,ar7,ai7,ar8,ai8,ar9,ai9,ar10,ai10,ar11,ai11,ar12,ai12,ar13,ai13,ar14,ai14,ar15,ai15,ar16,ai16);
  input [31:0]b;
  //input clk;
  output [31:0]ar1,ai1,ar2,ai2,ar3,ai3,ar4,ai4,ar5,ai5,ar6,ai6,ar7,ai7,ar8,ai8,ar9,ai9,ar10,ai10,ar11,ai11,ar12,ai12,ar13,ai13,ar14,ai14,ar15,ai15,ar16,ai16;
  modulationqpskRX m1(b[1:0],ar1,ai1);
  modulationqpskRX m2(b[3:2],ar2,ai2);
  modulationqpskRX m3(b[5:4],ar3,ai3);
  modulationqpskRX m4(b[7:6],ar4,ai4); 
  modulationqpskRX m5(b[9:8],ar5,ai5);
  modulationqpskRX m6(b[11:10],ar6,ai6);
  modulationqpskRX m7(b[13:12],ar7,ai7);
  modulationqpskRX m8(b[15:14],ar8,ai8);
  modulationqpskRX m9(b[17:16],ar9,ai9);
  modulationqpskRX m10(b[19:18],ar10,ai10);
  modulationqpskRX m11(b[21:20],ar11,ai11);
  modulationqpskRX m12(b[23:22],ar12,ai12);  
  modulationqpskRX m13(b[25:24],ar13,ai13);
  modulationqpskRX m14(b[27:26],ar14,ai14);
  modulationqpskRX m15(b[29:28],ar15,ai15);
  modulationqpskRX m16(b[31:30],ar16,ai16);
endmodule

module modulationqpskRX(bo,ar,ai);
  input [1:0]bo;
  //input clk;
  output reg[31:0]ar,ai;
always@(bo)
begin
  case(bo)
    2'b00:
    begin
      ar=32'b00111111001101010000010010000001;   //+0.707
      ai=32'b00111111001101010000010010000001;  //+0.707
    end
    2'b01:
    begin 
  
       ar=32'b00111111001101010000010010000001;  //+0.707
       ai=32'b10111111001101010000010010000001; //-0.707              
    end
    2'b10:
    begin     
       ar=32'b10111111001101010000010010000001;  //-0.707
       ai=32'b00111111001101010000010010000001; //+0.707      
    end
    2'b11:
    begin      
       ar=32'b10111111001101010000010010000001;   //-0.707
       ai=32'b10111111001101010000010010000001;  //-0.707             
    end
  endcase 
end
endmodule

////////////////////////////////end of transmitter block///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

////////////////////////////////channel////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
module channel(ar1,ai1,ar2,ai2,ar3,ai3,ar4,ai4,ar5,ai5,ar6,ai6,ar7,ai7,ar8,ai8,ar9,ai9,ar10,ai10,ar11,ai11,ar12,ai12,ar13,ai13,ar14,ai14,ar15,ai15,ar16,ai16,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15,r16,i1,i2,i3,i4,i5,i6,i7,i8,i9,i10,i11,i12,i13,i14,i15,i16);
  //input clk;
  input [31:0]ar1,ai1,ar2,ai2,ar3,ai3,ar4,ai4,ar5,ai5,ar6,ai6,ar7,ai7,ar8,ai8,ar9,ai9,ar10,ai10,ar11,ai11,ar12,ai12,ar13,ai13,ar14,ai14,ar15,ai15,ar16,ai16;
  
wire [31:0]h1r=32'b00111111000010011010011010110101;	wire [31:0]h1i=32'b10111101111111100010100000100100;
wire [31:0]h2r=32'b00111111111010101011110100111100;	wire [31:0]h2i=32'b00111111101111101010111001111101;
wire [31:0]h3r=32'b11000000000100001001000000101110;	wire [31:0]h3i=32'b00111111101101000101101000011101;
wire [31:0]h4r=32'b00111111010111001011100100100100;	wire [31:0]h4i=32'b00111111101101010110011011001111;
wire [31:0]h5r=32'b00111110101000110011100111000001;	wire [31:0]h5i=32'b00111111001010111110011101101101;
wire [31:0]h6r=32'b10111111101001110110001010110111;	wire [31:0]h6i=32'b10111111100110101000111101011100;
wire [31:0]h7r=32'b10111110110111100000000011010010;	wire [31:0]h7i=32'b00111111001101111001101001101011;
wire [31:0]h8r=32'b00111110101011110110100101000100;	wire [31:0]h8i=32'b00111111110100001010101001100101;
wire [31:0]h9r=32'b01000000011001010000010010000001;	wire [31:0]h9i=32'b00111110111110100101000100011010;
wire [31:0]h10r=32'b01000000001100010011110111011001;	wire [31:0]h10i=32'b00111111100001000111000100001101;
wire [31:0]h11r=32'b10111111101011001100100110000110;	wire [31:0]h11i=32'b00111111001110100001011000011110;
wire [31:0]h12r=32'b01000000010000100011101111001101;	wire [31:0]h12i=32'b10111110100110110101011100111111;
wire [31:0]h13r=32'b00111111001110011011001111010000;	wire [31:0]h13i=32'b00111110100101100111101000010000;
wire [31:0]h14r=32'b10111101100000010011101010010011;	wire [31:0]h14i=32'b10111111010010011000110001111110;
wire [31:0]h15r=32'b00111111001101101111011010010100;	wire [31:0]h15i=32'b00111111011000110110111000101111;
wire [31:0]h16r=32'b10111110010100011110101110000101;	wire [31:0]h16i=32'b10111111100100101101010000101100;

wire [31:0]nr1=32'b10111111100010001101000110110111;	wire [31:0]ni1=32'b00111111100010111111000101000001;
wire [31:0]nr2=32'b10111111010011110011101101100100;	wire [31:0]ni2=32'b00111111100011011111110110001011;
wire [31:0]nr3=32'b11000000001111000110111101101001;	wire [31:0]ni3=32'b10111111010111010001101101110001;
wire [31:0]nr4=32'b00111111101110000001110101111110;	wire [31:0]ni4=32'b00111101100111101000001111100100;
wire [31:0]nr5=32'b00111110101001101000000010011101;	wire [31:0]ni5=32'b10111111100110110110011110100001;
wire [31:0]nr6=32'b10111111010000010100000100100000;	wire [31:0]ni6=32'b10111111100011101000011100101011;
wire [31:0]nr7=32'b00111111101011110110010111111110;	wire [31:0]ni7=32'b10111011110111101101001010001001;
wire [31:0]nr8=32'b10111111110110110001001001101111;	wire [31:0]ni8=32'b00111111110001000010110000111101;
wire [31:0]nr9=32'b10111101110100010100111000111100;	wire [31:0]ni9=32'b10111111010001010000101100001111;
wire [31:0]nr10=32'b10111110011101110011000110010000;	wire [31:0]ni10=32'b00111110101111100010100000100100;
wire [31:0]nr11=32'b00111110101000110110111000101111;	wire [31:0]ni11=32'b10111110011001110000001110110000;
wire [31:0]nr12=32'b00111110101000000011010001101110;	wire [31:0]ni12=32'b00111111100011110000011011110111;
wire [31:0]nr13=32'b10111111010111010110101000010110;	wire [31:0]ni13=32'b10111111100010110110011110100001;
wire [31:0]nr14=32'b10111100111101101001010001000110;	wire [31:0]ni14=32'b00111101000001011000011110010100;
wire [31:0]nr15=32'b10111110001010001101101110001100;	wire [31:0]ni15=32'b00111111000011010111000010100100;
wire [31:0]nr16=32'b00111111001000001011000011110010;	wire [31:0]ni16=32'b00111111100011001110000001110110;

    output [31:0]r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15,r16;
    output [31:0]i1,i2,i3,i4,i5,i6,i7,i8,i9,i10,i11,i12,i13,i14,i15,i16;
    
trans t1(ar1,ai1,h1r,h1i,nr1,ni1,r1,i1);
trans t2(ar2,ai2,h2r,h2i,nr2,ni2,r2,i2);
trans t3(ar3,ai3,h3r,h3i,nr3,ni3,r3,i3);
trans t4(ar4,ai4,h4r,h4i,nr4,ni4,r4,i4);
trans t5(ar5,ai5,h5r,h5i,nr5,ni5,r5,i5);
trans t6(ar6,ai6,h6r,h6i,nr6,ni6,r6,i6);
trans t7(ar7,ai7,h7r,h7i,nr7,ni7,r7,i7);
trans t8(ar8,ai8,h8r,h8i,nr8,ni8,r8,i8);
trans t9(ar9,ai9,h9r,h9i,nr9,ni9,r9,i9);
trans t10(ar10,ai10,h10r,h10i,nr10,ni10,r10,i10);
trans t11(ar11,ai11,h11r,h11i,nr11,ni11,r11,i11);
trans t12(ar12,ai12,h12r,h12i,nr12,ni12,r12,i12);
trans t13(ar13,ai13,h13r,h13i,nr13,ni13,r13,i13);
trans t14(ar14,ai14,h14r,h14i,nr14,ni14,r14,i14);
trans t15(ar15,ai15,h15r,h15i,nr15,ni15,r15,i15);
trans t16(ar16,ai16,h16r,h16i,nr16,ni16,r16,i16);
endmodule

module trans(af,bf,cf,df,nr,ni,out_real,out_imag);
  
  input [31:0]af,bf;//transmitted values
  input [31:0]cf,df;//channel co-effiecients
  input [31:0]nr,ni;
  

  wire [31:0]noise_r,noise_i;
  
  output [31:0]out_real,out_imag;
 wire [31:0]x1,x2,x,y,z,r1,r2,i1;
  
  
  //noise variance
  parameter [31:0]var=32'b00000000000000000000000000000000; // no noise (ideal ccase)
  //parameter [31:0]var=32'b00111101110011001100110011001101 ; //var=0.1
  //parameter [31:0]var=32'b00111111100000000000000000000000 ;//var=1
  //parameter [31:0]var=32'b01000001001000000000000000000000 ;//var=10
  //parameter [31:0]var=32'b01000001111111001111100111011011; //var=31.622
                            

 
  fpmul m1(nr,var,noise_r);
  fpmul m2(ni,var,noise_i);  
  
  fpadd a1(af,bf,x1);                  //complex multiplication
  fpadd a2(cf,{~df[31],df[30:0]},x2);
  fpmul m3(x1,x2,x);
  fpmul m4(bf,cf,y);
  fpmul m5(af,df,z);
  
  fpadd a3(y,{~z[31],z[30:0]},r1);
  fpadd a4(x,{~r1[31],r1[30:0]},r2);
  fpadd a5(r2,noise_r,out_real);
  
  fpadd a6(y,z,i1);
  fpadd a7(i1,noise_i,out_imag);
endmodule

////////////////////////////////////////////receiver block///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//precomputation of data words and multiplying it with the results obtained from the receiver

module rec(clk,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15,r16,i1,i2,i3,i4,i5,i6,i7,i8,i9,i10,i11,i12,i13,i14,i15,i16,wout,xout,yout,zout);
 input clk; 
 input [31:0]r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15,r16,i1,i2,i3,i4,i5,i6,i7,i8,i9,i10,i11,i12,i13,i14,i15,i16;
 reg [31:0] data_1 [1:16];
 reg [31:0] data_2 [1:16];
 reg [31:0] data_3 [1:16];
 reg [31:0] data_4 [1:16];
      
 wire [31:0]yr1,yr2,yr3,yr4,yr5,yr6,yr7,yr8,yr9,yr10,yr11,yr12,yr13,yr14,yr15,yr16;
 wire [31:0]yi1,yi2,yi3,yi4,yi5,yi6,yi7,yi8,yi9,yi10,yi11,yi12,yi13,yi14,yi15,yi16;
 
 
 wire [31:0]rww1,rww2,rww3,rww4,rww5,rww6,rww7,rww8,rww9,rww10,rww11,rww12,rww13,rww14,rww15,rww16;
 wire [31:0]rxx1,rxx2,rxx3,rxx4,rxx5,rxx6,rxx7,rxx8,rxx9,rxx10,rxx11,rxx12,rxx13,rxx14,rxx15,rxx16;
 wire [31:0]ryy1,ryy2,ryy3,ryy4,ryy5,ryy6,ryy7,ryy8,ryy9,ryy10,ryy11,ryy12,ryy13,ryy14,ryy15,ryy16;
 wire [31:0]rzz1,rzz2,rzz3,rzz4,rzz5,rzz6,rzz7,rzz8,rzz9,rzz10,rzz11,rzz12,rzz13,rzz14,rzz15,rzz16;
 
 output [31:0]wout,xout,yout,zout;
 
 
 
 //known h parameter of channel estimation (no error - ideal)
wire [31:0]h1r=32'b00111111000010011010011010110101;	wire [31:0]h1i=32'b00111101111111100010100000100100;
wire [31:0]h2r=32'b00111111111010101011110100111100;	wire [31:0]h2i=32'b10111111101111101010111001111101;
wire [31:0]h3r=32'b11000000000100001001000000101110;	wire [31:0]h3i=32'b10111111101101000101101000011101;
wire [31:0]h4r=32'b00111111010111001011100100100100;	wire [31:0]h4i=32'b10111111101101010110011011001111;
wire [31:0]h5r=32'b00111110101000110011100111000001;	wire [31:0]h5i=32'b10111111001010111110011101101101;
wire [31:0]h6r=32'b10111111101001110110001010110111;	wire [31:0]h6i=32'b00111111100110101000111101011100;
wire [31:0]h7r=32'b10111110110111100000000011010010;	wire [31:0]h7i=32'b10111111001101111001101001101011;
wire [31:0]h8r=32'b00111110101011110110100101000100;	wire [31:0]h8i=32'b10111111110100001010101001100101;
wire [31:0]h9r=32'b01000000011001010000010010000001;	wire [31:0]h9i=32'b10111110111110100101000100011010;
wire [31:0]h10r=32'b01000000001100010011110111011001;	wire [31:0]h10i=32'b10111111100001000111000100001101;
wire [31:0]h11r=32'b10111111101011001100100110000110;	wire [31:0]h11i=32'b10111111001110100001011000011110;
wire [31:0]h12r=32'b01000000010000100011101111001101;	wire [31:0]h12i=32'b00111110100110110101011100111111;
wire [31:0]h13r=32'b00111111001110011011001111010000;	wire [31:0]h13i=32'b10111110100101100111101000010000;
wire [31:0]h14r=32'b10111101100000010011101010010011;	wire [31:0]h14i=32'b00111111010010011000110001111110;
wire [31:0]h15r=32'b00111111001101101111011010010100;	wire [31:0]h15i=32'b10111111011000110110111000101111;
wire [31:0]h16r=32'b10111110010100011110101110000101;	wire [31:0]h16i=32'b00111111100100101101010000101100;


wire [31:0]h1ic={~h1i[31],h1i[30:0]};
wire [31:0]h2ic={~h2i[31],h2i[30:0]};
wire [31:0]h3ic={~h3i[31],h3i[30:0]};
wire [31:0]h4ic={~h4i[31],h4i[30:0]};
wire [31:0]h5ic={~h5i[31],h5i[30:0]};
wire [31:0]h6ic={~h6i[31],h6i[30:0]};
wire [31:0]h7ic={~h7i[31],h7i[30:0]};
wire [31:0]h8ic={~h8i[31],h8i[30:0]};
wire [31:0]h9ic={~h9i[31],h9i[30:0]};
wire [31:0]h10ic={~h10i[31],h10i[30:0]};
wire [31:0]h11ic={~h11i[31],h11i[30:0]};
wire [31:0]h12ic={~h12i[31],h12i[30:0]};
wire [31:0]h13ic={~h13i[31],h13i[30:0]};
wire [31:0]h14ic={~h14i[31],h14i[30:0]};
wire [31:0]h15ic={~h15i[31],h15i[30:0]};
wire [31:0]h16ic={~h16i[31],h16i[30:0]};


transRX t1(r1,i1,h1r,h1ic,yr1,yi1);
transRX t2(r2,i2,h2r,h2ic,yr2,yi2);
transRX t3(r3,i3,h3r,h3ic,yr3,yi3);
transRX t4(r4,i4,h4r,h4ic,yr4,yi4);
transRX t5(r5,i5,h5r,h5ic,yr5,yi5);
transRX t6(r6,i6,h6r,h6ic,yr6,yi6);
transRX t7(r7,i7,h7r,h7ic,yr7,yi7);
transRX t8(r8,i8,h8r,h8ic,yr8,yi8);
transRX t9(r9,i9,h9r,h9ic,yr9,yi9);
transRX t10(r10,i10,h10r,h10ic,yr10,yi10);
transRX t11(r11,i11,h11r,h11ic,yr11,yi11);
transRX t12(r12,i12,h12r,h12ic,yr12,yi12);
transRX t13(r13,i13,h13r,h13ic,yr13,yi13);
transRX t14(r14,i14,h14r,h14ic,yr14,yi14);
transRX t15(r15,i15,h15r,h15ic,yr15,yi15);
transRX t16(r16,i16,h16r,h16ic,yr16,yi16); 

initial
begin
  $readmemb("RPB1-realoutput.txt", data_1);
  $readmemb("RPB2-realoutput.txt", data_2);
  $readmemb("RPB3-realoutput.txt", data_3);
  $readmemb("RPB4-realoutput.txt", data_4);
end

assign rww1=data_1[1];
assign rww2=data_1[2];
assign rww3=data_1[3];
assign rww4=data_1[4];
assign rww5=data_1[5];
assign rww6=data_1[6];
assign rww7=data_1[7];
assign rww8=data_1[8];
assign rww9=data_1[9];
assign rww10=data_1[10];
assign rww11=data_1[11];
assign rww12=data_1[12];
assign rww13=data_1[13];
assign rww14=data_1[14];
assign rww15=data_1[15];
assign rww16=data_1[16];


assign rxx1=data_2[1];
assign rxx2=data_2[2];
assign rxx3=data_2[3];
assign rxx4=data_2[4];
assign rxx5=data_2[5];
assign rxx6=data_2[6];
assign rxx7=data_2[7];
assign rxx8=data_2[8];
assign rxx9=data_2[9];
assign rxx10=data_2[10];
assign rxx11=data_2[11];
assign rxx12=data_2[12];
assign rxx13=data_2[13];
assign rxx14=data_2[14];
assign rxx15=data_2[15];
assign rxx16=data_2[16];


assign ryy1=data_3[1];
assign ryy2=data_3[2];
assign ryy3=data_3[3];
assign ryy4=data_3[4];
assign ryy5=data_3[5];
assign ryy6=data_3[6];
assign ryy7=data_3[7];
assign ryy8=data_3[8];
assign ryy9=data_3[9];
assign ryy10=data_3[10];
assign ryy11=data_3[11];
assign ryy12=data_3[12];
assign ryy13=data_3[13];
assign ryy14=data_3[14];
assign ryy15=data_3[15];
assign ryy16=data_3[16];


assign rzz1=data_4[1];
assign rzz2=data_4[2];
assign rzz3=data_4[3];
assign rzz4=data_4[4];
assign rzz5=data_4[5];
assign rzz6=data_4[6];
assign rzz7=data_4[7];
assign rzz8=data_4[8];
assign rzz9=data_4[9];
assign rzz10=data_4[10];
assign rzz11=data_4[11];
assign rzz12=data_4[12];
assign rzz13=data_4[13];
assign rzz14=data_4[14];
assign rzz15=data_4[15];
assign rzz16=data_4[16];


  sumofproducts A1(rww1,rww2,rww3,rww4,rww5,rww6,rww7,rww8,rww9,rww10,rww11,rww12,rww13,rww14,rww15,rww16,wout);
  sumofproducts A2(rxx1,rxx2,rxx3,rxx4,rxx5,rxx6,rxx7,rxx8,rxx9,rxx10,rxx11,rxx12,rxx13,rxx14,rxx15,rxx16,xout);
  sumofproducts A3(ryy1,ryy2,ryy3,ryy4,ryy5,ryy6,ryy7,ryy8,ryy9,ryy10,ryy11,ryy12,ryy13,ryy14,ryy15,ryy16,yout);
  sumofproducts A4(rzz1,rzz2,rzz3,rzz4,rzz5,rzz6,rzz7,rzz8,rzz9,rzz10,rzz11,rzz12,rzz13,rzz14,rzz15,rzz16,zout);
endmodule

module transRX(af,bf,cf,df,out_real,out_imag); //complex multiplication submodule
  input [31:0]af,bf;//received sigals
  input [31:0]cf,df;//conjugate channel co-effiecients
  output [31:0]out_real,out_imag;
 wire [31:0]x1,x2,x,y,z,r1,r2,i1;
 fpadd a1(af,bf,x1);
 fpadd a2(cf,{~df[31],df[30:0]},x2);
  fpmul m3(x1,x2,x);
  fpmul m4(bf,cf,y);
  fpmul m5(af,df,z);
  fpadd a3(y,{~z[31],z[30:0]},r1);
  fpadd a4(x,{~r1[31],r1[30:0]},out_real);
  fpadd a6(y,z,out_imag);
endmodule


module sumofproducts(rw1s,rw2s,rw3s,rw4s,rw5s,rw6s,rw7s,rw8s,rw9s,rw10s,rw11s,rw12s,rw13s,rw14s,rw15s,rw16s,wout);
  
input[31:0]rw1s,rw2s,rw3s,rw4s,rw5s,rw6s,rw7s,rw8s,rw9s,rw10s,rw11s,rw12s,rw13s,rw14s,rw15s,rw16s;

output [31:0]wout;

wire [31:0]w1s,w2s,w3s,w4s,w5s,w6s,w7s,w8s,w9s,w10s,w11s,w12s,w13s,w14s,w15s,w16s; 
wire [31:0]wout1,wout2,wout3,wout4,wout5,wout6,wout7,wout8;
wire [31:0]wout11,wout22,wout33,wout44;
wire [31:0]wout111,wout222;

   fpadd a17(rw1s,rw2s,wout1);
   fpadd a18(rw3s,rw4s,wout2);
   fpadd a19(rw5s,rw6s,wout3);
   fpadd a20(rw7s,rw8s,wout4);
   fpadd a21(rw9s,rw10s,wout5);
   fpadd a22(rw11s,rw12s,wout6);
   fpadd a23(rw13s,rw14s,wout7);
   fpadd a24(rw15s,rw16s,wout8);
       
      fpadd a25(wout1,wout2,wout11);   
      fpadd a26(wout3,wout4,wout22);
      fpadd a27(wout5,wout6,wout33);
      fpadd a28(wout7,wout8,wout44);
        
      fpadd a29(wout11,wout22,wout111);   
      fpadd a30(wout33,wout44,wout222); 
      
      fpadd a31(wout111,wout222,wout);
endmodule

module compare(wout,xout,yout,zout,detected_data);
  input [31:0]wout,xout,yout,zout;
  output reg [31:0]detected_data;
  reg [31:0]CFItemp1,CFItemp2;
  reg [31:0]temp1,temp2,temp3;
  always @ (wout,xout,yout,zout)
  begin
    if(wout[31] == 0 && xout[31]== 0)
      begin
        if(wout[30:23]>xout[30:23])
    begin     
     temp1=wout;
     CFItemp1=32'b01101101101101101101101101101101;
    end
  else if(wout[30:23]<xout[30:23])
    begin
     temp1=xout;
     CFItemp1=32'b10110110110110110110110110110110;
    end   
  else
    begin
      if (wout[22:0]>xout[22:0])
        begin
          temp1=wout;
          CFItemp1=32'b01101101101101101101101101101101;
        end
     else
       begin
          temp1=xout;
          CFItemp1=32'b10110110110110110110110110110110;
        end
    end
  end
else if (wout[31]==1 && xout[31]==0)
  begin
    if(wout[30:23]>xout[30:23])
    begin     
     temp1=xout;
     CFItemp1=32'b10110110110110110110110110110110;
    end
  else if(wout[30:23]<xout[30:23])
    begin
     temp1=xout;
     CFItemp1=32'b10110110110110110110110110110110;
    end   
  else
    begin
      if (wout[22:0]>xout[22:0])
        begin
          temp1=xout;
          CFItemp1=32'b10110110110110110110110110110110;
        end
     else
       begin
          temp1=wout;
          CFItemp1=32'b01101101101101101101101101101101;
        end
    end
  end
  else if(wout[31]==0 && xout[31]==1)
    begin
      if(wout[30:23]>xout[30:23])
    begin     
     temp1=wout;
     CFItemp1=32'b01101101101101101101101101101101;
    end
  else if(wout[30:23]<xout[30:23])
    begin
     temp1=wout;
     CFItemp1=32'b01101101101101101101101101101101;
    end   
  else
    begin
      if (wout[22:0]>xout[22:0])
        begin
          temp1=wout;
          CFItemp1=32'b01101101101101101101101101101101;
        end
     else
       begin
          temp1=xout;
          CFItemp1=32'b10110110110110110110110110110110;
        end
    end
  end
  else if(wout[31]==1 && xout[31]==1)
    begin
      if(wout[30:23]<xout[30:23])
    begin     
     temp1=wout;
     CFItemp1=32'b01101101101101101101101101101101;
    end
  else if(wout[30:23]>xout[30:23])
    begin
     temp1=xout;
     CFItemp1=32'b10110110110110110110110110110110;
    end   
  else
    begin
      if (wout[22:0]<xout[22:0])
        begin
          temp1=wout;
          CFItemp1=32'b01101101101101101101101101101101;
        end
     else
       begin
          temp1=xout;
          CFItemp1=32'b10110110110110110110110110110110;
        end
    end
    end
    if(yout[31] == 0 && zout[31]== 0)
      begin
        if(yout[30:23]>zout[30:23])
    begin     
     temp2=yout;
     CFItemp2=32'b11011011011011011011011011011011;
    end
  else if(yout[30:23]<zout[30:23])
    begin
     temp2=zout;
     CFItemp2=32'b00000000000000000000000000000000;
    end   
  else
    begin
      if (yout[22:0]>zout[22:0])
        begin
          temp2=yout;
          CFItemp2=32'b11011011011011011011011011011011;
        end
     else
       begin
          temp2=zout;
          CFItemp2=32'b00000000000000000000000000000000;
        end
    end
  end
else if (yout[31]==1 && zout[31]==0)
  begin
    if(yout[30:23]>zout[30:23])
    begin     
     temp2=zout;
     CFItemp2=32'b00000000000000000000000000000000;
    end
  else if(yout[30:23]<zout[30:23])
    begin
     temp2=zout;
     CFItemp2=32'b00000000000000000000000000000000;
    end   
  else
    begin
      if (yout[22:0]>zout[22:0])
        begin
          temp2=zout;
          CFItemp2=32'b00000000000000000000000000000000;
        end
     else
       begin
          temp2=yout;
          CFItemp2=32'b11011011011011011011011011011011;
        end
    end
  end
  else if(yout[31]==0 && zout[31]==1)
    begin
      if(yout[30:23]>zout[30:23])
    begin     
     temp2=yout;
     CFItemp2=32'b11011011011011011011011011011011;
    end
  else if(yout[30:23]<zout[30:23])
    begin
     temp2=yout;
     CFItemp2=32'b11011011011011011011011011011011;
    end   
  else
    begin
      if (yout[22:0]>zout[22:0])
        begin
          temp2=yout;
          CFItemp2=32'b11011011011011011011011011011011;
        end
     else
       begin
          temp2=zout;
          CFItemp2=32'b00000000000000000000000000000000;
        end
    end
  end
  else if(yout[31]==1 && zout[31]==1)
    begin
      if(yout[30:23]<zout[30:23])
    begin     
     temp2=yout;
     CFItemp2=32'b11011011011011011011011011011011;
    end
  else if(yout[30:23]>zout[30:23])
    begin
     temp2=zout;
     CFItemp2=32'b00000000000000000000000000000000;
    end   
  else
    begin
      if (yout[22:0]<zout[22:0])
        begin
          temp2=yout;
          CFItemp2=32'b11011011011011011011011011011011;
        end
     else
       begin
          temp2=zout;
          CFItemp2=32'b00000000000000000000000000000000;
        end
    end
    end
    
    if(temp1[31] == 0 && temp2[31]== 0)
      begin
        if(temp1[30:23]>temp2[30:23])
    begin     
     temp3=temp1;
     detected_data=CFItemp1;//2'b01;
    end
  else if(temp1[30:23]<temp2[30:23])
    begin
     temp3=temp2;
     detected_data=CFItemp2;//2'b10;
    end   
  else
    begin
      if (temp1[22:0]>temp2[22:0])
            begin
              temp3=temp1;
            detected_data=CFItemp1;//2'b01;
            end
            else     
          begin
            temp3=temp2;
           detected_data=CFItemp2;//2'b10;
        
    end
  end
  end
  
  

else if (temp1[31]==1 && temp2[31]==0)
  begin
    if(temp1[30:23]>temp2[30:23])
    begin     
     temp3=temp2;
     detected_data=CFItemp2;//2'b10;
    end
  else if(temp1[30:23]<temp2[30:23])
    begin
     temp3=temp2;
     detected_data=CFItemp2;//2'b10;
    end   
  else
    begin
      if (temp1[22:0]>temp2[22:0])
        begin
          temp3=temp2;
          detected_data=CFItemp2;//2'b10;
        end
     else
       begin
          temp3=temp1;
          detected_data=CFItemp1;//2'b01;
        end
    end
  end
  else if(temp1[31]==0 && temp2[31]==1)
    begin
      if(temp1[30:23]>temp2[30:23])
    begin     
     temp3=temp1;
     detected_data=CFItemp1;//2'b01;
    end
  else if(temp1[30:23]<temp2[30:23])
    begin
     temp3=temp1;
     detected_data=CFItemp1;//2'b01;
    end   
  else
    begin
      if (temp1[22:0]>temp2[22:0])
        begin
          temp3=temp1;
          detected_data=CFItemp1;//2'b01;
        end
     else
       begin
          temp3=temp2;
          detected_data=CFItemp2;//2'b10;
        end
    end
  end
  else if(temp1[31]==1 && temp2[31]==1)
    begin
      if(temp1[30:23]<temp2[30:23])
    begin     
     temp3=temp1;
     detected_data=CFItemp1;//2'b01;
    end
  else if(temp1[30:23]>temp2[30:23])
    begin
     temp3=temp2;
    detected_data=CFItemp2;//2'b10;
    end   
  else
    begin
      if (temp1[22:0]<temp2[22:0])
        begin
          temp3=temp1;
          detected_data=CFItemp1;//2'b01;
        end
     else
       begin
          temp3=temp2;
          detected_data=CFItemp2;//2'b10;
        end
    end
    end 
    end   
    
endmodule
  
//floating point adder

module fpadd(a,b,out);
  input [31:0]a,b;
  output [31:0]out;
  
  wire [7:0]e1,e2,ex,ey,exy,ex1,ey1,ex2,ex3;
  wire s1,s2,s,s3,sr,sn,s4,sx1,sy1,sn1,sn2,sn3,sn4,sr1,sr2,sn5,sn6;
  wire [23:0]m1,m2,mx,my,mxy,mx1,my1;
  wire [24:0]mxy1,mxy2;
  assign s1=a[31];
  assign s2=b[31];
  assign e1=a[30:23];
  assign e2=b[30:23];
  assign m1[23]=1'b1;
  assign m2[23]=1'b1;
  assign m1[22:0]=a[22:0];
  assign m2[22:0]=b[22:0];
  //submodule for compare and shfit
  cmpshift as(e1[7:0],e2[7:0],s1,s2,m1[23:0],m2[23:0],clk,ex,ey,mx,my,s,sx1,sy1);
 
  //submodule for mantissa addition snd subtraction
  faddsub as1(mx,my,sx1,sy1,s,ex,clk,mxy1,ex2,sn3,sn4,s3,sr1);
 
  //sub module for normalization
    normalized as2(mxy1,sr1,sn3,sn4,s3,clk,ex,sr,exy,mxy);
  assign out={sr,exy,mxy[22:0]};
endmodule



module normalized(mxy1,s,s1,s2,s3,clk,ex,sr,exy,mxy);
  input[24:0]mxy1;
  input s,s1,s2,s3,clk;
  input[7:0]ex;
  output reg sr;
  output reg[7:0]exy;
  output reg[23:0]mxy;
  reg [24:0]mxy2;
  always@(*)
  begin
    sr=s?s1^(mxy1[24]&s3):s2^(mxy1[24]&s3);
    mxy2=(mxy1[24]&s3)?~mxy1+25'b1:mxy1;
    mxy=mxy2[24:1];
    exy=ex;
    repeat(24)
    begin
      if(mxy[23]==1'b0)
        begin
          mxy=mxy<<1'b1;
          exy=exy-8'b1;
        end
      end
    end
endmodule
    
//submodule for addition or subtraction
module faddsub(a,b,s1,s2,sn,ex1,clk,out,ex2,sn3,sn4,s,sr1);
  input [23:0]a,b;
  input[7:0]ex1;
  input s1,s2,clk,sn;
  output reg [7:0]ex2;
  output reg[24:0]out;
  output reg s,sn3,sn4,sr1;
  always@(*)
  begin
    ex2=ex1;
    sr1=sn;
    sn3=s1;
    sn4=s2;
    s=s1^s2;
    if(s)
      begin
        out=a-b;
      end
    else
      begin
        out=a+b;
      end
    end
  endmodule
    
//module for copare &shift
module cmpshift(e1,e2,s1,s2,m1,m2,clk,ex,ey,mx,my,s,sx1,sy1);
  input [7:0]e1,e2;
  input [23:0]m1,m2;
  input clk,s1,s2;
  output reg[7:0]ex,ey;
  output reg[23:0]mx,my;
  output reg s,sx1,sy1;
  reg [7:0]diff;
  always@(*)
  begin
    sx1=s1;
    sy1=s2;
    if(e1==e2)
      begin
        ex=e1+8'b1;
        ey=e2+8'b1;
        mx=m1;
        my=m2;
        s=1'b1;
      end
    else if(e1>e2)
      begin
        diff=e1-e2;
        ex=e1+8'b1;
        ey=e1+8'b1;
        mx=m1;
        my=m2>>diff;
        s=1'b1;
      end
    else
      begin
        diff=e2-e1;
        ex=e2+8'b1;
        ey=e2+8'b1;
        mx=m2;
        my=m1>>diff;
        s=1'b0;
      end
    end
  endmodule

//floating point multiplier
module fpmul(a,b,out);
 
  input[31:0]a,b;
  output [31:0]out;
  
  wire [7:0]exp;
  wire [22:0]mant;
  wire s;
  
 fmul manipulate(a[30:23],b[30:23],a[31],b[31],{1'b1,a[22:0]},{1'b1,b[22:0]},exp,mant,s);
 assign out={s,exp,mant}; //concatenation
endmodule
   
//submodule for multiplication
module fmul(aexp,bexp,as,bs,am,bm,exp,mant,s);
  
  input [23:0]am,bm;
  input[7:0]aexp,bexp;
  input as,bs;
  
  output reg [7:0]exp;
  output reg[22:0]mant;
  output reg s;
  reg flag; //zero flag
  reg [7:0]ex;
  reg [8:0]e;
  reg [47:0]man;
  
  always@(*)
  begin
    if(((aexp==0)||(bexp==0))&&((am[22:0]==0)||(bm[22:0]==0))) //check for zero operand
     begin 
      exp=0;
      mant=0;
      s=0;
      flag=1;
    end
  else
    begin
      s=as^bs; //sign 
      e=aexp+bexp; //exponent
      ex=e-127;
     
      man=am*bm;  //mantissa
     flag=0;
    end
  
  //normalise
 if(~flag) 
  if(man[47]==0)
    begin
      mant=man[45:23]; //truncate and have only 23 bits from MSB
      exp=ex;
    end
  else
    begin
      mant=man[46:24];
      exp=ex+1;
    end
  end
endmodule

The text files consist of 16 real values of 32bit each..Help me why there is no timing information encountered?

sharath666 · Jan 19, 2015

Have you given any constraints? We get these messages only if constraints are not given..

ads-ee · Jan 19, 2015

The OP appears to not have any edge triggered block anywhere that I noticed. Of couse it won't have any timing information. No surprise there.

This code is totally rubish, it's probably the worst I've ever seen.

You need to read a Verilog book and relearn from scratch.

mrflibble · Jan 19, 2015

ads-ee said:
This code is totally rubish, it's probably the worst I've ever seen.

I don't know if it's the worst I've ever seen, but it certainly is, uhm .. interesting. It is however a nice all in one collection of What Not To Do items, so I saved it in the anti-pattern folder.

As for the OP's question:

Minimum period: No path found
...
How can this be possible..

As sharath666 already pointed out, no constraints were specified.

Pointing out what is wrong in the above code is going to take a bit too long, so I'll limit it to the very top part.

Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
module sisored(clk,transmitted_data,detected_data);
    input clk;
    input [31:0]transmitted_data;
    output [31:0]detected_data;
    wire [31:0]wout,xout,yout,zout;    
    wire [31:0]r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15,r16;
    wire [31:0]i1,i2,i3,i4,i5,i6,i7,i8,i9,i10,i11,i12,i13,i14,i15,i16;
    wire [31:0]ar1,ai1,ar2,ai2,ar3,ai3,ar4,ai4,ar5,ai5,ar6,ai6,ar7,ai7,ar8,ai8,ar9,ai9,ar10,ai10,ar11,ai11,ar12,ai12,ar13,ai13,ar14,ai14,ar15,ai15,ar16,ai16;
   
    assign transmitted_data=32'b01101101101101101101101101101101;

1 - You are probably from the land of delicious curries, in which case you learned it this way ... but the rest of the world uses verilog-2001 (ANSI) port declarations.
2 - transmitted_data is declared as an input, so what do you think the assign transmitted_data=32'b01101101101101101101101101101101; statement is going to do?
3 - all those r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15,r16 etc wires are a bad idea. Better to use an array. Because if you don't your code is going to be horribly unreadable and unmaintainable.
4 - see 3. You will probably run into other problems due to verilog limitations, but there are reasonable solutions for that. These solutions are not perfect, but IMO they are definitely better than the current 457862348 wires approach.

For a quick intro on what I mean with "use verilog-2001 (ANSI) port declarations", please see:
**broken link removed**
https://www.asic-world.com/verilog/verilog2k1.html

ads-ee · Jan 19, 2015

ISE reports maximum frequency timing information when there is no constraint file. The problem the OP is seeing is because the design turns into this after synthesis:

There are no paths to time with or without a constraint file.

All the i# and r# signals aren't connected to anything so synthesis removed all the logic as none of it is driven.

- - - Updated - - -

Besides that, the RTL has latches, since there are no edge sensitive always blocks. ISE reports 160 of them after initial synthesis, prior to optimizing away everything.

- - - Updated - - -

mrflibble said:
I don't know if it's the worst I've ever seen, but it certainly is, uhm .. interesting. It is however a nice all in one collection of What Not To Do items, so I saved it in the anti-pattern folder.

Are you sure it's not the worst or at least a contender?

It's has pretty much every NEVER DO THAT coding style that you can ever imagine.
1. pre-2001 (in 2015) port declarations
2. port mapping by position.
3. no comments/useless comments e.g. assign out={s,exp,mant}; //concatenation
4. excessive line lengths (keep it under 80-100)
5. lack of useful whitespace (readability)
6. horrid naming conventions (actually none that I can see)
7. using binary for all constants?
8. magic constants that should have been declared as local parameters (preferred) or as defines.
9. LATCHES! (always @(*) mxy=mxy<<1'b1

10. plethora of unused signals (don't you edit unused stuff out of your code?)
11. a clock that never gets used and should be used!
12. hierarchical boundaries should be rethought
13. lack of array usage
14. lack of generate usage
15. Typically I've found when nested if statements get like the compare code it means you are doing something wrong (it's more than 400 lines of nested if statements)

I'm sure I could come up with more, but I'm not going to go past the obvious ones.

Welcome to EDAboard.com

Timing information during synthesis

shobanaganesan

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sharath666

Advanced Member level 2

ads-ee

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mrflibble

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