And here is the following timing diagram for the code:
I get how the Hardware goes back to zero when strobe is asserted. But how do I know when strobe is asserted from the code? Why does it get asserted when Hardware = "10"? and why does the Hardware only count to "10" instead of "11"? I am trying to practice making timing diagrams from VHDL code. Also I do not know why SIGOUT is asserted in the timing diagram from the code. Some explanation would help me greatly!
Cool I get that now! One more question, why does SIGOUT delayed from Strobe in the timing diagram? In the second process it asserts that SIGOUT(or IntNet) goes high when Strobe goes high so shouldn't they be asserted at the same time?
IntNet is the registered version of Strobe (i.e. a 1-clock delayed version of Strobe). Near the beginning of the architecture IntNet is assigned to SIGOUT.
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Hmmm, just noticed the entity is called MIDTERM2 and the architecture is prob1.
I sure hope you aren't trying to cheat on your exam.