Since all blocks are driven by same clock GLA, when I use 50Mhz PLL I have this kind of error as you see above. When I try with 100Mhz, that is the frequency I should use, I have in addition this kind of error when I simulate compiled code:
** Warning: */IOPAD_TRI PULSE WIDTH High VIOLATION ON D;
#
# Expected := 5 ns; Observed := 4.959 ns; At : 68324.973 ns
# Time: 68324973 ps Iteration: 1 Instance: /testbench/Buff_0/\GLA_pad/U0/U0\
As you adviced I've added this:
"create_clock -name {GLA} -period 10.000000 -waveform {0.000000 5.000000} PLLClock_0/Core:GLA"
But I've also 8 warnings on inferred clocks, why this since I use one clock source? In particular one tells "Found inferred clock Counter|NU_5_inferred_clock which controls 148 sequential elements. This clock has no specified timing constraint which may adversely impact design performance."
Another warning I have that is related to the fourth signal is this "Latch generated from process for signal EN; possible missing assignment in an if or case statement."
This are warning I thinks are related to above timing delays.
I've a questions about this:
- This problems are solvible by timing constraints or by correcting code?
- Is possible to solve this problems by setting timing costraints without change code?