Timing Constraints :Xilinx

[cmos babe]

Hey everyone,

My life story:
I've been lost within the user guides and reference manuals trying to figure out how to understand the timing related stuff in FPGA but I failed. For example, when I read the timing constraints in XST guide, there were references to things in the constraints guide, when I read the constraints guide thing I found more new terms then I started reading about TRACE and I got more confused.

My questions:

a) Why are timing constraints important ?
b) can a design work without them?
c) what's the starting point of understanding all these timing stuff, what are the main constraints that I should know well .
d) is there a step by step approach that I can follow to be sure that no hold/setup violations will occur?

I hope that the experts here help me because I will still have more questions and I'm working on a complex project..

Thank you all.

 

[no_mad]

hi cmos babe,

1. Why timing constraint is important?

ans: to make sure ur design can meet the target spec (usually target frequency). In another words, no timing violations.

2. can a design work without them?

ans: No.

3. what's the starting point of understanding all these timing stuff, what are the main constraints that I should know well .

ans: In my opinion, lecture notes and books on timing analysis are the best starting point. Then, u need to get ur hands on the design. Write a small design (verilog/vhdl or gate, up to u), synthesize and perform timing analysis. Read the timing report and analyze. Try to understand from the timing report and if u faced any probs u can discuss in this group or ask from experience dude in ur company.

The main constraints are clock, input delay and output delay perhaps loads and drive strength too.

4. is there a step by step approach that I can follow to be sure that no hold/setup violations will occur?

ans: This advice was told to me by an experience dude (a good friend of mine) during my first experience in FPGA design. I still ask these Qs to myself even ASIC design.
1. check all the clock constraints (if u have multiple clocks)
2. how the fsm implemented?
-> if can, use one-hot encoding
3. how about the fan-out?
4. have u set limits on the fan-out?
-> large capacitance may mess up
5. how about the architecture level?
After asking these Qs to urself, moving to the physical level would be warranted.


Therefore, all these are only a small contribution from an intermediate engineer . Please do give comments &/ suggestions. Anyway, we all still learning and it will not never stop.

Good luck and enjoy

-no_mad

 

[echo47]

The Xilinx docs are overwhelming to new folks. You are not alone!

Your design may work fine without any timing constraints. If you run the timing analyzer, it tells you how fast the chip will go. If that meets your requirements, then you are done. If it's not fast enough, then you can apply timing constraints, and the place/route will try to meet them.

I try to use synchronous logic everywhere, including all my I/O pads. Normally I need only one timing constraint - PERIOD applied to my clock input. That takes care of all my synchronous logic, including sections clocked by DCMs that I sometimes use to synthesize special clock frequencies and phases. If XST warns me that it can't meet my constraint for some reason, I examine the timing report to find the troublesome area, and then modify my design by inserting pipeline stages or whatever I think will help.

Sometimes I have critical I/O signals that need special attention, so the OFFSET constraint is useful too. But most of the time I can find a simple synchronous solution between the FPGA's natural I/O timing and the external chip it's talking to.