Timing circuit with NOR gates

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Jester

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Can someone explain how the diode-resistor portion of this circuit works?

Note:

1) The schematic was determined by “beeping out” the traces on an existing PCB so there is a chance I missed something.

2) I used a 100:1 probe for the D1 signal to minimize loading.

 

Here is a normal Cmos oscillator circuit:
 

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