timing analyzing of gated clock

[honeyxyb]

set_clock_gating_check

Hi ,all:
I am using clock gating mathdology on power saving. Because I have no
integrated clock gating cell , so I use 4 standcell (latch , and , or , inv ) to buildup
one gating cell, in Design compiler , I can analyze setup and hold timing for clock gating logic:
dc_shell-t> report_timing -to core/mac_core/csr/clk_gate_tx_cnt7_cnt_reg/main_gate/A

****************************************
Report : timing
-path full
-delay max
-max_paths 1
Design : L001
Version: V-2004.06-SP2
Date : Fri Sep 16 14:34:24 2005
****************************************

# A fanout number of 1000 was used for high fanout net computations.

Operating Conditions: nom_pvt Library: ss_gen_max_cap
Wire Load Model Mode: top

Startpoint: core/mac_core/csr/clk_gate_tx_cnt7_cnt_reg/latch
(positive level-sensitive latch clocked by clk_125m')
Endpoint: core/mac_core/csr/clk_gate_tx_cnt7_cnt_reg/main_gate
(gating element for clock clk_125m)
Path Group: clk_125m
Path Type: max

Point Incr Path
--------------------------------------------------------------------------
clock clk_125m' (rise edge) 3.20 3.20
clock network delay (ideal) 0.00 3.20
core/mac_core/csr/clk_gate_tx_cnt7_cnt_reg/latch/CK (TLATX1)
0.00 3.20 r
core/mac_core/csr/clk_gate_tx_cnt7_cnt_reg/latch/Q (TLATX1)
0.15 3.35 r
core/mac_core/csr/clk_gate_tx_cnt7_cnt_reg/main_gate/A (AND2X1)
0.00 3.35 r
data arrival time 3.35

clock clk_125m (rise edge) 6.40 6.40
clock network delay (ideal) 0.00 6.40
core/mac_core/csr/clk_gate_tx_cnt7_cnt_reg/main_gate/B (AND2X1)
0.00 6.40 r
clock gating setup time -1.00 5.40
data required time 5.40
--------------------------------------------------------------------------
data required time 5.40
data arrival time -3.35
--------------------------------------------------------------------------
slack (MET) 2.05




But , in primetime , I cannot analyze timing for gated logic , I have use
the following command to set the requirement :
set_clock_gating_check -setup 1 -hold 1 [all_clock]
when I use report_timing command , it report as :
No constrained paths .

I think primetime should infer gated clock automaticlly.


So Can anyone help me? Thanks in advance.

 

[patrickli]

clock gating check

if you use power compiler insert clock-gating, use
propagate_constraints -gate_clock
it can add clock-gating check . otherwise you need add:
set_clock_gating_check -rise -hold 0 [get_cells {..../main_gate}]

 

[rakeshnunna]

clock gating timing check

Hi ,

PT cannot infer some type of gated clocks.But it will give a Warning that a gated clock is not inferred.

You have a variable to set the mode of clock gating checks"Sta_derive_clock_mode".Switch the mode to auto mode.


I think this will solve your problem.

Regards