want2LearnVlsi
Newbie level 6
verilog timescale directive
Hi,
Why the directive `timescale should be used?
Suppose if we donot use the 'timescale directive, and mention the delays like #10, etc, how the simlator will consider it?
KSSR
Hi,
Why the directive `timescale should be used?
Suppose if we donot use the 'timescale directive, and mention the delays like #10, etc, how the simlator will consider it?
KSSR