In 8051 single machine cycle consists of 12 clock cycles and timers incremented once per every machine cycle. So a running timer will be incremented:
for OSC_FREQ/OSC_PER_INST times per second.So the time for each increment is OSC_PER_INST/OSC_FREQ.
where OSC_FREQ is the clock frequency and OSC_PER_INST is 12.
In 8052 all timers are up couting timers. To generate interrupt for 20 milliseconds, the count to be
loaded is 0xFFFF - (20 milli seconds / (OSC_PER_INST/OSC_FREQ).
which equals 63536 - ((20 milli seconds * OSC_FREQ) / OSC_PER_INST)
which equals 63536 - ((20 * OSC_FREQ) / OSC_PER_INST) if OSC_FREQ is defined in KHZ
for example if we take OSC_FRQ as 12 mhz, in this case 1 millisecond needs 1000 increments.
so for 20 milliseconds it is 20000. So the macro is correct for 20 milliseconds.
I am confused with other macroes, if OSC_FREQ & OSC_PER_INST are fixed, they can not be correct up to my knowledge. Simple one is for 10 milliseconds it should be 10 not 100.
#define T_15ms (66536 - (tWord) ((OSC_FREQ * 67 ) / (OSC_PER_INST)))
will becorrect if changed to
#define T_15ms (66536 - (tWord) ((OSC_FREQ / 67 ) / (OSC_PER_INST)))
#define T_50micros (66536 - (tWord) ((OSC_FREQ / 26000) / (OSC_PER_INST)))
will be correct if changed to
#define T_50micros (66536 - (tWord) ((OSC_FREQ / 20000) / (OSC_PER_INST)))
#define T_10ms (66536 - (tWord) ((OSC_FREQ * 100 ) / (OSC_PER_INST)))
will be correct if changed to
#define T_10ms (66536 - (tWord) ((OSC_FREQ / 100 ) / (OSC_PER_INST)))
for all of the above macroes OSC_FREQ is in HZ
The logic is
15 milliseconds is 67th part of a second. 1000 / 15 = 66.66666667.
10 milliseconds is 100th part of a second. 1000 / 10 = 100
50 milliseconds is 20000th part of a second 1000000 / 50 = 20000
But this gives timing difference beacuse of rounding 66.666667 to 67
If 20 milliseconds macro also to be iwritten in same way it is
#define T_20ms (63536 - ((OSC_FREQ / 50) / OSC_PER_INST))
as 20 milliseconds is 50th part of a second, 1000/20 = 50
Please let me now If I am wrong or there is some hidden logic.
Cheers