With technology shrinking every few years, more and more gates are being packed into silicon. Chips are partitioned in tiles, where tiles are synthesized separately.
1) What is the average tile size these days of chip having more than a billion gates?
2) Does Synopsys/Cadence put a limit in their tools as to how many cells/gates they can synthesize in a tile?
When I was in the business of designing chips, I was asked to do an FPGA synthesis. When I ran it on my Intel machine, it crashed. I ran it on the companies x86 server and it took 30 hours. The x86 server processor was running at 3.0 GHz and had lots of RAM and hard disk. When I ran the same job on a Sun Sparc station it took 30 minutes. The Sun sparc station had a 1 Ghz processor and much less RAM and Hard Drive.
3) Why the difference?
4) Since Sun has left the business, what machines are used to synthesize and place and route Billion gate chips these days?
5) When I looked at the Synopsys/Cadence websites, they only seem to offer support for RedHat Linux on x86 and IBM and IBM AIX. Is IBM power9 the machine widely used for backend ASIC work now? How much better is the Power9 than an Intel/AMD x86 server?