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Tie Low & tie High

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Oct 10, 2007
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pls give me information about tie Low & Tie High

Dear dude,

The gate of transistor may turn on or turn –off due to power and ground bounce.

Due to this problem occurs. So if a gate has to turn on only on VDD it must be brought near Pcells. This is called Tie_high

similarly if a gate has to turn off only on Vss it must be brought near N_cells. This is called Tie_low.

This Pcells and Ncells are a part of Standard cell library.

Tie-high and Tie-Low cells are used to connect the gate of the transistor to either power or ground. In deep sub micron processes, if the gate is connected to power/ground the transistor might be turned on/off due to power or ground bounce. The suggestion from foundry is to use tie cells for this purpose. These cells are part of standard-cell library. The cells which require Vdd, comes and connect to Tie high...(so tie high is a power supply cell)...while the cells which wants Vss connects itself to Tie-low

Hello Phutaneshv

I am unable to understand this statement
So if a gate has to turn on only on VDD it must be brought near Pcells. This is called Tie_high ???
wts this Pcells and Ncells

Tie-hi and Tie-low is usually provided as a standard cell. If not, you can opt to make one yourself.

The reason these exist is to provide some kind of shielding for the logic 1 and logic 0 metal lines. Tying these nets directly to VDD and GND can cause various issues (as others noted, ground bouncing). It's not necessary in many cases if you trust your regulator and/or your design is sufficiently small that there isn't that much coupling capacitance on your ground line but it's usually a good idea.

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