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Tie-high and Tie-Low cells are used to connect the gate of the transistor to either power or ground. In deep sub micron processes, if the gate is connected to power/ground the transistor might be turned on/off due to power or ground bounce. The suggestion from foundry is to use tie cells for this purpose. These cells are part of standard-cell library. The cells which require Vdd, comes and connect to Tie high...(so tie high is a power supply cell)...while the cells which wants Vss connects itself to Tie-low
Tie-hi and Tie-low is usually provided as a standard cell. If not, you can opt to make one yourself.
The reason these exist is to provide some kind of shielding for the logic 1 and logic 0 metal lines. Tying these nets directly to VDD and GND can cause various issues (as others noted, ground bouncing). It's not necessary in many cases if you trust your regulator and/or your design is sufficiently small that there isn't that much coupling capacitance on your ground line but it's usually a good idea.