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Thyristor Gate Drive

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Member level 5
Jul 22, 2014
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I'm having trouble interpreting fig 8 in the datasheet below. Any one know of any docs that walk though these type graphs?

Does the Gate Voltage (Y axis) mean the actual drop (Gate to Cathode) of the device? In the top left, what do the resistances relate to.

My application is DC capacitor discharge using parallel devices so I need fast/matched turn on. Anyone seen any docs that relate to that? I'm trying to piece it together using what I've found but its a bit of a challenge.


Couldn't say, sorry. Maybe top left refers to load of 30 or 65 ohms at 20V. I searched for 'thyristor capacitor discharge circuit', 'Optically Triggered Thyristor for Capacitor Discharge Applications' pdf and 'AN4607' pdf by STMicro were among the results and might be of interest if not already read.
It depends on the peak current you are trying to put thru the device.

For that one, it should be 300mA min, into the gate, to guarantee firing at 0 deg C, if you are paralleling SCR's - then you should have a small air cored inductor in the output of each to guarantee the same rise time of current in each SCR - this is important. ( 100A / uS per device max )

The ideal gate firing pulse is about 1A for 10uS, then falling to 300mA for the remainder of the time.

The rise time of gate current should be the same for each device

The voltages and resistances given in small type in the graphs are the gate drive voltages and series resistance to the gate for the given di/dt, i.e. full and 30%

Each device has an internal resistor G - Kathode, to help keep it off for fast rising dv/dt after a turn off - you can measure this with a DVM - ohms. If your external circuit has fast rising dv/dt after or during turn off - then you should arrange a mosfet to clamp the gate to kathode in the OFF time - < 1 ohm mosfet ( 50V or higher ).
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Regarding the di/dt.... In unclear about if you can slow the AK di/dt by lowering the gate drive current - take the two examples on the graph for example. (i.e. is it a bit like slowing the gate drive on a FET)
Do you have to select gate current to meet your max known di/dt (given the external circuitry) to protect the device / turn on properly....

Feels a bit like the chicken and egg question.

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