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[SOLVED] Three Stage LDO (Low Drop Out Regulator)

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nitishn5

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Hi All,

I have been working on the following architecture for a three stage LDO.

arch.png

This is a Three stage LDO with a single miller capacitance compensation using inverted current buffers. The first stage is a basic pmos input differential error amplifier. The second stage is like a unity gain buffer. The third stage is the pass transistor.

This is a simpler version of the architecture used in **broken link removed** Another similar paper is **broken link removed**

The problem that I am facing is the presence of a pair of complex poles beyond UGB. While the complex poles and associated phase change does not affect the stability of the LDO, it causes ringing in the output during load and line transients. It also gives rise to a complex peak in the PSRR curve.

I have tried solving for the transfer function to figure out from where the complex pole comes from but the transfer functions are orders to handle. I can find out the dominant pole and this matches the one expected from the miller splitting. But the complex pole is still a mystery.

The architecture has two loops. One within the other. One is the outer loop through the three stages and the resistor divider. The other is from the output through the compensation capacitor, the current mirror and the 2nd and 3rd stage back to the output. I feel that the presence of the two loops is giving rise to the complex poles.

Can anyone help me in figuring out from where the complex poles come from and what can be done to remove its effect.
All help will be appreciated.
 

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