Thin/thick gate N+/psub diodes

[mvigna]

Hello everybody,
I would like to understand the difference between thin gate N+/Psub and thick gate N+/Psub diodes.
According to the PDK manual they are made of the same layers but a "dualgate" layer present in the thick gate diode.

Now, since a diode has not any gate oxide, I assume that such a "dualgate" layer has to affect somehow the doping level and/or the doping depth in these two devices. How?

I'd like to have more explanation about this.

Thank you all for your help!

Mat

 

[dick_freebird]

The dopings should be unaffected, but evidently these
are "gated diodes" and/or poly-defined, self aligned
(not mask defined at the N+ / active layers). Then
you have the reverse voltage reliability "pinned" by
the thin ox or thick ox's hot carrier and oxide breakdown
limitations, probably lower than the raw junction
capability. Thin ox probably has ratings like core FETs
and thick ox, similar to I/O / ESD devices (of which,
the thick ox diode is probably one standard device).

 

[mvigna]

Hi and thank you for your answer!
I don't get what the role of the oxide is in the diodes. According to the layout the diodes simply consists of a n+ layer, a marker layer and (only in the thick gate diode) the dualgate layer and therefore the diodes should be simple n+/p junctions.

Am I missing something?

Thanks!

 

[dick_freebird]

In that case I see no valuable distinction. Other than,
perhaps, some slightly different charge trapping which
can affect leakage floor pre- and post-zap, etc.

 

[mvigna]

I think there should be some important difference between them. Considering that they have different breakdown voltage values the doping levels must be differents as well...i'd like to get a deeper insight on this...

 

[mvigna]

Up please! :grin:

 

[erikl]

Can you show a cross-section of the dualgate layer diode layout?

 

[mvigna]

Hi Erikl! Unfortunately I have no cross-section available...but according to the process manual such a dualgate layer is used for thick gate MOSFETs. I wonder what this has to do with diodes...
By the way the technology is GF/chartered 0.13um CMOS logic/Mixed Signal/RF

Thank you for your help!

 

[erikl]

... according to the process manual such a dualgate layer is used for thick gate MOSFETs. I wonder what this has to do with diodes...

There is a method to extend the depletion region width at the curved edge of a pn-junction (which defines the breakdown voltage of the device) by properly designed and supplied metal guardrings over oxide (i.e. gates). Such a guardring influences a corresponding counter-charge at the SiO₂-Si interface, which - by proper positioning and supply - can extend the depletion region width, hence the breakdown voltage.

I have seen such a construction to realize high voltage transistors - also with multiple concentric guardrings over different oxide steps. So if you have dual gate oxide layers available, you could make profit of this method to achieve higher breakdown voltages.

Use an inner gate ring with thin oxide, an outer one over thick oxide. Of course you should know the doping concentration of the lower doped side in order to calculate the ring dimension(s).

Sorry I can't find an appropriate reference paper.