the way to generate register

[skycanny]

hi,all guys. Is there any way to generate regisers in CPLD or FPGA except using "signal" and "DFF" instantiation?

Any help would be appreciated!

 

[Iouri]

What is wrong woith using "signal", or what are trying to impliment?

 

[gliss]

You might be able to instantiate the vendors RAM in the device directly.

 

[salma ali bakr]

well...u can make a register urself,
see this code:

///////////////////////////////////////////////////////////////////////////////////////////
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

---------------------------------------------------

entity reg is

generic(n: natural :=2);
port( I: in std_logic_vector(n-1 downto 0);
clock: in std_logic;
load: in std_logic;
clear: in std_logic;
Q: out std_logic_vector(n-1 downto 0)
);
end reg;

----------------------------------------------------

architecture behv of reg is

signal Q_tmp: std_logic_vector(n-1 downto 0);

begin

process(I, clock, load, clear)
begin

if clear = '0' then
-- use 'range in signal assigment
Q_tmp <= (Q_tmp'range => '0');
elsif (clock='1' and clock'event) then
if load = '1' then
Q_tmp <= I;
end if;
end if;

end process;

-- concurrent statement
Q <= Q_tmp;

end behv;


/////////////////////////////////////////////////////////////////////////////////////////

(u can change it according to ur needs, u don't have to have all these inputs for instance, i hope that is what u want)

best regards,
Salma

 

[SynKore Support]

This is the version in verilog, FYI:



reg Q;
always @ ( negedge Rst_n or posedge Clk ) begin
if( !Rst_n )
Q <= 1'b0;
else if( En )
Q <= D_In;
end



Michael Zhang

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[ananth_anbu]

Hi ur answer helpful me too . ple tell me how to instantiate the vendors RAM in the device directly?

 

[eelinker]

In the name of God
a non-recomended way of register generation is using asynchronous method.plz don't use this method,althought it is described in brown and veransic digital logic text book.
regards