Re: The Verilog PLI is Dead (maybe) Long Live the SystemVeri
I went to a design verification seminar. When the host asked what simulars people use. About 70% of the audience voted for m/o/d/e/l/s/i/m, 30% of them c/a/d/e/n/c/e n/c/s/i/m. None of the audience uses V/C/S. Does this tell you something?
In my opinion, except for the synthesis tools, there is really no a lot s/y/n/o/p/s/y/s can claim dominance. However, encounter rtl compiler is emerging, magma is taking away market shares. Even synplicify asic is becoming more competative.
Sutherland is not a designer. He makes his living by teaching/training. If everybody is happy and familiar with verilog, people like him have to do something new.
As a language for design, systemverilog offers little new. As a language for verification, it's way too weak than competative HVLs. That's the conclusion I drew after attending 3 systemverilog seminars offered by s/y/n/ops/y/s.