The Verilog PLI is Dead (maybe) Long Live the SystemVerilog

[jimjim2k]

Hi

I have found the title of an award-winning paper
from SUNG San Jose 2004:

"The Verilog PLI is Dead (maybe) Long Live the SystemVerilog"


Please search for it:

1. h**p://www.snug-universal.org/papers/papers.htm

* -> t



Who has it?
Who readed it?


tnx

 

[radix]

Re: The Verilog PLI is Dead (maybe) Long Live the SystemVeri

jimjim2k,

My acct recently expired. However, I am interested in the paper as well so I've sent an email to a buddy of mine who still has an acct. Once he sends it I'll post it unless someone else beats me to it.

Radix

 

[eternal_nan]

Re: The Verilog PLI is Dead (maybe) Long Live the SystemVeri

Here you go...

 

[farmerwang]

Re: The Verilog PLI is Dead (maybe) Long Live the SystemVeri

Synopsys sucks, as you may noticed, the best paper winners always advertise synopsys tools.

 

[eternal_nan]

Do you mind elaborating on why Synopsys sucks ??? I find Synopsys tools to be overall better than the competition (Cadence), both in the sense of usability and quality of results. Of course that SyNopsys User Group (SNUG) papers will be concentrated on synopsys tools...

 

[rx300]

Re: The Verilog PLI is Dead (maybe) Long Live the SystemVeri

I went to a design verification seminar. When the host asked what simulars people use. About 70% of the audience voted for m/o/d/e/l/s/i/m, 30% of them c/a/d/e/n/c/e n/c/s/i/m. None of the audience uses V/C/S. Does this tell you something?
In my opinion, except for the synthesis tools, there is really no a lot s/y/n/o/p/s/y/s can claim dominance. However, encounter rtl compiler is emerging, magma is taking away market shares. Even synplicify asic is becoming more competative.
Sutherland is not a designer. He makes his living by teaching/training. If everybody is happy and familiar with verilog, people like him have to do something new.
As a language for design, systemverilog offers little new. As a language for verification, it's way too weak than competative HVLs. That's the conclusion I drew after attending 3 systemverilog seminars offered by s/y/n/ops/y/s.