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The Verification Language trend is Systemverilog

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rake

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systemverilog with vcs

:arrow:we all know that,but where can i find the reference paper about it?
BTW,which vendor support SV better?mentor or synopsys or cadence?
 

rake said:
:arrow:we all know that,but where can i find the reference paper about it?

Several books/papers exist, a good colelction is @ www.synopsys.com/systemverilog

Mentor's web site also has several nice papers on this topic. As far as I see, Cadence is behind in SV support, but you better check with your CDN support.

BTW, I have co-authored 2 books in relevance to your query:

1. SVA Handbook, www.abv-sva.org
2. Pragmatic Approach to VMM adoption, www.systemverilog.us

HTH
Ajeetha, CVC
www.noveldv.com
* A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5 h**p://www.systemverilog.us/
* SystemVerilog Assertions Handbook
* Using PSL/Sugar
 

Synopsys and Mentor support SV fully and all new simulators from them are
compatible with SV
 

Yes.... any vendor is fine if you are starting now.

But if you are already a user of Specman - e and trying to migrate to SV, then you better look at Synopsys as they have something more than SV itself... something called as "SV extensions" which can help u in migrating from e to SV.

Best Regards,
Harish
https://hdlplanet.tripod.com
https://groups.yahoo.com/group/hdlplanet
 

cadence is better. there are many bug in synopsys vcs.
 

Mentors tool QuestaSim 6.3 is stable for SV Verification...
 

gaonkc said:
cadence is better. there are many bug in synopsys vcs.

can you specify your experience on VCS and why you think its buggy tool ?
 

can you specify your experience on VCS and why you think its buggy tool ?

The person's post was made in 2006. Today, VCS is no more buggy than Incisive or Modelsim :) which means, not so many bugs that you can't use the tool...but it still has just enough bugs that you want to pay for maintenance contract to get latest versions whenever they are released :)

Seriously, at one point, VCS was far ahead in Systemverilog support. Today, the competition has almost caught up, and offer comparable support for Systemverilog features. None of them is 100% compliant with every detail of Systemverilog, and VCS still holds a slight lead, but any of the big 3 simulators are stable enough to use in a new, large Systemverilog design/verification-environment.
 

you can use electromaniacs.com for getting some good books on systemverilog
 

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