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Want to design an asynchronous FIFO?
Once I designed a parametric width converter asynchronous FIFO, for Virtex-II FPGA. the design principles does not change for ASIC or FPGA designs.
The FIFO contains three main parts: read controller, write controller, and a dual port memory. Dual port memory cores are available by both FPGA and ASIC manufacturer vendors. read controller and write controller modules are almost the same. e.g. a good read controller should have empty and readCounter output signals. write controller has full and writeCounter outputs. there are read enable and write enable control signals for writing data to and reading data from fifo. There are two modules that generate the dual port's read and write addresses. after each read or write these counters will point to the next memory location. Now the main problem is generating Empty and Full signals. there should be clock synchronizers to transfer fifo status data between read and write clock domains.
In the google, please search for "Clifford E. Cummings" he has written some very good articles for asynchronous designs, which you can download from his site.
ramo asked me to describe it more, so here it is:
First, take care that we are talking about two different clocks, their positive edges can be placed any where and with any possbile delay. So synchronizers are a must. Now, the ASIC/FPGA manufacturer should design it's flip flops so that they can recover to a stable state, if they got metastable. you know that metastability causes when an input signal to a flip flop changes in the setup time interval of that flip flop.
Now both read controller and write controller should have a status register. suppose that our fifo has four places to store data. (Suppose that our fifo is not width converter for now) then there should be 4 bits status registers for both read and write controller. now when a packet is written in the first place of memory, we will set the first bit of status register in the write controller to 1, then when a new packet comes and fills the second place, we will set the second bit of the status register. when one packet is read from memory we will set the first bit of status register in the read controller. now simply we will send the write controller status register to read controller (we will transfer data from Write clock domain to read clock domain) and then the resultant read counter is the xor of these two status registers. again, the status register in the read controller will be transfered to write clock domain and then will be xored with write controller status register and the result is what we call write counter. when all of the xored bits are 1, we say fifo is full. and in the read clock domain, when all of the bits of the xored status registers is zero we say fifo is empty. take care that fifo full signal is generated in the write clock domain and fifo read is generated in the read clock domain.
Fifo latancy in setting Full or Empty or read/write counters is important. with the above structure, Full signal should go high, immediately after fifo becomes full, without any latency. but it will come down with some delays because when you begin reading from fifo, your read operation effect should go through synchronizer flip flops first and then it reaches to write controller. Again, suppose that you are reading from fifo, and it becomes empty, Empty output signal should go high with no latency. but when you write new data to fifo , Empty will not come down immediately.
readCounter and writeCounter latencies depend on the width of the fifo. they have a typical latency of 2 or 3 cycles. take care of the meaning of latency, here we hace two clocks.