the race in digital circuit

[wowo1215]

Hi All,
Anybody can help me to explain the sentence below, why this config can lead to race-free operation? Thanks.

"To ensure race-free operation, changes on TAP inputs (TMS and TDI) are clocked into the test logic defined by this standard on the rising edge of TCK while changes at the TAP output (TDO) occur on the falling edge of TCK"

from Pg20 of IEEE1149.1

 

[sivamit]

Hi All,
Anybody can help me to explain the sentence below, why this config can lead to race-free operation? Thanks.

"To ensure race-free operation, changes on TAP inputs (TMS and TDI) are clocked into the test logic defined by this standard on the rising edge of TCK while changes at the TAP output (TDO) occur on the falling edge of TCK"

from Pg20 of IEEE1149.1

Read this...

http://www.interfacebus.com/Logic_Design_Race_Conditions.html


-Sharon

 

[wowo1215]

Thanks, Sharon.
I know what cause a race,but the question is: why the method indicated can avoid race?

 

[sivamit]

Thanks, Sharon.
I know what cause a race,but the question is: why the method indicated can avoid race?

I think it is because there is a sufficient amount time for the inputs to settle down(TCLK/2) before the output voltage is allowed to change(after TCLK/2). i.e if all the inputs cannot arrive at the processing unit at the same time, u should not manipulate output with only few inputs.
i.e read everything -then process the output.

Let's wait for others' reply