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the question of high frequent CTS?

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emma0252

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bufmaxtran

there is a clock with period 2ns.
it is divided and create clk1 and clk2. clk1 period is 40ns, clk2 period is 32ns.
.ctstch文件中是这么定义的
maxdelay 2ns
mindelay 0ns
maxskew 50ps
sinkmaxtran 150ps
bufmaxtran 150ps

But after CTS, the rise phase delay is 3ns, it is too long than 2ns.
what wrong with?
 

shelby

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1) Check which buffers you are allowing CTS to use. You may be able to give it faster buffers (even SVT/LVT at a cost of leakage power)

2) Check the logic in your clock lines. If you have dividers + a lot of other logic, it might be hard to meet the 2ns due to the design itself.

3) Check the physical placement and routing of the clock tree. If you have hard macros, check where clock pin enters, you may be able to move the clock pin or even move the macro itself for better timing.

4) If your design is large, you can break the clock tree up to debug where CTS is having trouble meeting maxdelay. Start defining separate clocks for different parts of your design in the ctscth file and leave them unbalanced. Then you can see which parts of your design are having trouble meeting 2ns. This may help debugging of #2
 

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