the question about fpga's system clock

[magma1981]

i am a new guy

i want to know the fpga's system clock and the ranges of output & input frequency

from the datasheet, but i don't know which part can find the information?


somebody can tell me ?

thanks a lot!!

 

[Johnson]

Which vendor and what FPGA do you mean?

For Xilinx and its new product, V4, operating frequency can be high as 450MHz. But at all it depends on your design and device speed grade!

Hope 2 help!

 

[magma1981]

altera and xilinx companies

can we get the informations of frequency from the datasheet or just the

experience?

 

[echo47]

With FPGA design, the individual flip-flops do have a maximum speed capability (it's usually specified in the data sheet, like Johnson's example), but the overall maximum clock speed depends heavily on your design, layout, and particular FPGA part number. When you run the place-and-route tools, it will tell you the maximum reliable speed. If that speed meets your needs, then you are done. If not, then you can ask the tools to try to route the chip to achieve your specified speed. You may need to redesign your logic (more pipelining or whatever) to help the tools produce a faster layout.

 

[indianarcher]

Dear ,

The FPGA system clock can be an external clock source . Now it depends on you that you want to use this external clock as system clock or you pass it through clock manipulation and management components ( like DCM in XilinX SP3, V4 etc.) to have
a derived clock as FPGA system clock . In any case you can not have any system clock which is more the the clock speed which the FPGA silicon can support. Also when
you manipulate clock with DCM you get two frequency modes HIGH and Low and they
have some specific range based on Device Family.